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博客园 - bullfinch

Notes of "The Unbridged Pentium 4" - Pentium 4 Road Map Notes of "The Unbridged Pentium 4" - Overview of the Processor Role Notes of "Pentium Processor System Architecture" - Pentium Signal Interface (part) Notes of "Pentium Processor System Architecture" - Mutiple Processors and the MESI Model Notes of "Pentium Processor System Architecture" - The Functional Units & Pentium Cache Overview AMD Opteron Architecture related Fedora Core 3 挂载FAT32分区以及中文显示和输入 摄像头设置事件 linux下安装HP NC6000无线网卡(HP W500) C#学习笔记(八) TreeView.AfterCheck和TreeNode.Checked赋值的问题 C#学习笔记(七) C#学习笔记(六) C#学习笔记(五) 图像中密集点群的定位 C#学习笔记(四) 中兴ZXDSL831立式蓝猫自动拨号+NAT+DHCP设置 关于变参(zz) C#学习笔记(三)
Notes of "The Unbridged Pentium 4" - Pentium 4 System Overview
bullfinch · 2005-05-27 · via 博客园 - bullfinch

1. PCI Express the Root Complex plays the role that used to be played by the Memory Control Hub(MCH), or the North Bridge. It also incorporates te system memory controller (rather than residing the system memory controller on FSB). This affects the behavior of snoop of memory access initited by a device adapter (which  is under the Root Complex). The graphic adapter(GFX) is connected to the Root Complex, take the place of the AGP.

2. The Boot Strap Processor (BSP) is the processor that starts fetching, decoding and executing instructions at startup time. Taskes:

  • Power-On Self-Test(POST)
  • Performing the initial configuration of the platfrm components including the BSP
  • Detecting the presence of other processors
  • Configuring the APs(Application Processors)
  • Making entries in the ACPI table for all of the processors as well as their Local APICs
  • Booting the OS startup code into memory and the passing control to the OS startup code.


3. An MP OS assigns a task to a processor in the following manner:

  • Typically, it instructs a disk controller to load a task into memory.
  • Once the task is in memory, the OS kernel executing on the BSP causes the BSP's Local APIC to issue a SIPI(Startup Inter Processor Interrupt message) to one of the other processors over the FSB bus. The start address of the program just placed in memory is supplied in this message packet.
  • Upon receipt of the SIPI, the target processor leaves the wait-for-IPI state and begins to fetch and execute the task in memory.