1. The Pentium processor address bus consits of two sets of signal lines:
2. A20 Mask(A20M#) allows the processor to emulate the address wrap-around at the 1MB boundary that occurs on the 8086/8088.
3. Address Translation:
4. A series of transceivers can do steering to pass data from one path to another when the device is smaller than 64-bits. (BRDY# will net be sent until all data is ready)
5. Bus Cycle Control Signals:
Address Status Output(ADS#)
Bus Cycle Definition(M/IO# D/C# W/R# CACHE#) Special Cycles(BE5:0#)
LOCK# and SCYC
......
6. The Pentium processor invalidates a cache line that is hit during a locked read transfer and runs the bus cycles to external memory.
7. Thre processor must respond to the BOFF# signal and external snoops during locked transfer.
8. Setting CD and NW bits to 0s enables the internal caches and places the data cache in the write-back mode.
9. When the WB/WT# line is set hight the cache line is stored in the E state causing it to behave according to ther write-back policy. When the WB/WT# line set low, the cache line is stored in S state, causing all writes to be transferred to external momery according to the write-through policy.
10. L2 cache use AHOLD to force the processor to remove its address and prepare to receive a snoop address over its address bus. AHOLD only is used in look-through cache with a L2 cache.
11. External logic must assert the EADS# signal to tell the processor that a valid address is on its local address bus and to go ahead and snoop it.
12. External logic also drives the INV signal along with EADS# to tell the processor whether to leave the cache line valid or to mark it invalid in case of a snoop hit.
13. The Pentium processor asserts the HIT# signal when a snoop hit occurs on one of its internal caches.
14. The Pentium processor asserts the HIT Modified Line(HITM#)signal to indicate that a snnop operation has hit to a modified line in cache.
15. The signal Page Cache Disable(PCD) signal controls cacheability of the L2 cache, while the Page Write-Through(PWT) signal specifies whether the L2 cache should use a write-back or write-through policy for the line being written to.
16. The FLUSH# signal causes the data in the internal caches to be invalidated. (After write-back)
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