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1. Pentium Processor has two instruction pipelines: "u" pipeline and "v" pipeline, they can work parallel.

2. Pentium Processor has seperated data cache and code cache to eliminates internal contention

3. There are 2 kinds of cache architectures: look-through cache and look-aside cache, the former one can bring performance benefits by allowing bus concurrency, but take disadvatage of lookup penalty when a cache miss happens.

4. Three write policies exsit to prevent the cache cosistency problem brought by a write hit:

• Write-Through Cache Designs
• Buffered Write-Through Cahce Designs(also get benefits when write misses happen)
• Write-Back Cache Designs

5. Other Bus Master will bring cache consistency problems while:

• Writes to memory (with write-through cache)
• Reads from memory (with write-back cache)
• Writes to main memory (with write-back cache) just invalite the line in cache is a mistake

6. Bus Snoop is used under below circumstances:

• Memory write by another bus master
      Invalidate the line
      Snarf the data
• Memory read by another bus master
      Write-back the line
      Supply data directly

7. L2 Cache begins to be employed in some 486 systems. L1 cache implements a write-through policy to the L2 cache to ensure the cache coherency between them

8. Pentium processor use write-back policy in its L1 data cache and support write-through or write back plicy on a line-by-line basis.

9. Write-Once Policy ensures that when a line is initially placed in the L1 data cache, it is marked as shared to force a write-throuth to the L2 cache upon the first internal write hit to that cache line.Subsequently write to this line will not be propagated through to the L2 cache. The coherency is ensured by the different state.

10. Memory writes initiated by another bus master hitting a L2 cache with a modified line will cause the L2 cache to backoff the bus master and snoop the L1 cache, write-back the modified line, then remove the backoff and let the master to complete its write.