- Addresses and helps reduce the real challenges and bottlenecks of system architectures
- Memory is directly connected to the CPU optimizing memory performance
- I/O is directly connected to the CPU for more balanced throughput and I/O
- CPUs are connected directly to CPUs allowing for more linear symmetrical multiprocessing
和
Integrated DDR DRAM Memory Controller
- Changes the way the processor accesses main memory, resulting in increased bandwidth, reduced memory latencies, and increased processor performance
- Available memory bandwidth scales with the number of processors
- 128-bit wide integrated DDR DRAM memory controller capable of supporting up to eight (8) registered DDR DIMMs per processor
- Available memory bandwidth up to 6.4 GB/s (with PC3200) per processor
以及
HyperTransport™ Technology
- Provides a scalable bandwidth interconnect between processors, I/O subsystems, and other chipsets
- Support of up to three (3) coherent HyperTransport links, providing up to 24.0 GB/s peak bandwidth per processor
- Up to 8.0 GB/s bandwidth per link providing sufficient bandwidth for supporting new interconnects including PCI-X, DDR, InfiniBand, and 10G Ethernet
- Offers low power consumption (1.2 volts) to help reduce a system’s thermal budget
两段，又去查了这两个技术的资料，HyperTransport的资料在www.hypertransport.org上，这个技术主要是提供更高的外部设备和CPU的连接带宽，而Direct Connect Architecture是无论如何也找不到其他资料了，只能凭这片语只字来猜测，是一种直连技术，将各种资源直接连接到处理器而不是通过总线互联。 根据Integrated DDR DRAM Memory Controller这个feature，AMD的确是把内存控制器集成到了芯片里面。这些资料可能各个硬件网站都已经很早就有了，只是我知道的比较晚，但是更进一步的资料，除了HyperTransport还有公开的以外，另两个都没有了。
最后，找到一个pdf，是Opteron和Xeon的对比，里面有架构的略图，放在下面： 
这样看来，这个架构似乎已经没有了“总线”的概念，与我以前在系统结构上学习的架构已经有很大的区别了...不知道为什么反响不大...还有，如果这是一种很好的架构的话，为什么没有引起仿效。