Single Processor MESI Implementation:
Initial Read from System Memory:(II)[SE] L2-E L2-WB/WT#=0 L1-S
First Write to the Internal Cache Line:(SE)[EM] L2-M L2-WB/WT#=1 L1-E (Write-Once Policy)
Bus Master Read from Line Stored in the M State in L2 Cache:(EM)[SE] L2-backoff-snoop L1(E) L2-INV=0 L1-S L2-Write Back-release backoff L2-E(/S)
Bys Master Write to a Line Stored In the M State in the L2 Cache:(EM)[II] L2-backoff-snoop L1(E) L2-INV=1 L1-I L2-Write Back-release backoff L2-I
Second and Subsequent Writes to the Internal Cache:(EM)[MM] L1-M (Write-Once Policy)
Bus Master Read from a Modified Line in the L1 Data Cache:(MM)[SE] L2-backoff-snoop L1(M) L1-Write Back L2-INV=0 L1-S L2-E(/S) L2-release backoff
Bus Master Write to a Modified Line in the L1 Cache:(MM)[II] L2-backoff-snoop L1(M) L1-Write Back L2-INV=1 L1-I L2-I L2-release backoff
* L1-S indicates that any update should be written through to L2
* (xx)indicates the state of L1 and L2 before transition
* [xx]indicates the state of L1 and L2 after transition
Multi Processor MESI Implementation:
Mulitmaster systems have to use write-back look-through caches to avoid overloading the bus with numerous accesses made by each bus master.And communication exists between the L2 cache controllers in order to indicate the result of snoop operations.
Read by Processor B from a Line Present in Processor A's Cache
A(SE)[SS]
B(II)[SS] AL2-S (no snoop AL1) AL2-CHIT#=0 BL2-S BL2-WB/WT#=0 BL1-S
A(EM)[SS]
B(II)[SS] AL2-CHIT#=0-CHITM#=0 BL2-BOFF#=0 AL2-snoop AL1(E) AL2-INV=0 AL1-S AL2-Write Back AL2-S AL2-CHIT#=1-CHITM#=1 BL2-BOFF#=1 AL2-CHIT#=0 BL2-S BL2-WB/WT#=0 BL1-S
A(MM)[SS]
B(II)[SS] AL2-CHIT#=0-CHITM#=0 BL2-BOFF#=0 AL2-snoop AL1(M) AL2-INV=0 AL1-Write Back AL1-S AL2-S AL2-CHIT#=1-CHITM#=1 BL2-BOFF#=1 AL2-CHIT#=0 BL2-S BL2-WB/WT#=0 BL1-S
Write by Processor B to a Line Present in Processor A's Cache
Scenario 1: Initial cache line state after reading target line from system memory. A(SE)[II]
B(II)[II] AL2-I AL2-snoop AL1(S) AL2-INV=1 AL1-I (B depends on allocate-on-write support)
A(EM)[II]
B(II)[II] AL2-CHIT#=0-CHITM#=0 BL2-BOFF#=0 AL2-snoop AL1(E) AL2-INV=1 AL1-I AL2-Write Back AL2-I A2-CHITM#=1 BL2-BOFF#=1
A(MM)[II]
B(II)[II] AL2-CHIT#=0-CHITM#=0 BL2-BOFF#=0 AL2-snoop AL1(M) AL2-INV=1 AL1-Write Back AL1-I AL2-I AL2-CHITM#=1 BL2-BOFF#=1
A(SS)[II]
B(SS)[SE] BL2-E AL2-I AL2-snoop AL1(S) AL2-INV=1 AL1-I
Table 1 L1 Cache State Changes During Momory Reads
|
Present State |
Pin Activity |
Next State |
Description |
|
M |
n/a |
M |
Read Hit. |
|
E |
n/a |
E |
Read Hit. |
|
S |
n/a |
S |
Read Hit. |
|
I |
CACHE#, KEN#, PWT low and WB/WT# high |
E |
Read Miss. L2 write-through or not present. |
|
I |
CACHE#, KEN# low, (WB/WT# low or PWT hight) |
S |
Read Miss. L2 write-back. |
|
I |
CACHE# or KEN# high |
I |
Read Miss. non-cacheable. |
Table 2 L1 Cache State Changes During Momory writes
|
Present State |
Pin Activity |
Next State |
Description |
|
M |
n/a |
M |
Write Hit. |
|
E |
n/a |
M |
Write Hit. |
|
S |
PWT low and WB/WT# high |
E |
Write Hit. L2 write-once |
|
S |
PWT, WB/WT# low |
S |
Write Hit. |
|
S |
PWT high |
S |
Write Hit. write-through page |
|
I |
n/a |
I |
Write Miss. write-through |
Table 3 L1 Cache State Changes During Read or Write Snoop
|
Present State |
Next State |
Next State |
Description |
|
M |
I |
S |
snoop hit to amodified line. |
|
E |
I |
S |
a snoop hit to clean line in exclusive state. |
|
S |
I |
S |
a snoop hit to a clean line in shared state. |
|
I |
I |
I |
snoop miss. |
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