惯性聚合 高效追踪和阅读你感兴趣的博客、新闻、科技资讯
阅读原文 在惯性聚合中打开

推荐订阅源

P
Proofpoint News Feed
Blog — PlanetScale
Blog — PlanetScale
GbyAI
GbyAI
C
Check Point Blog
腾讯CDC
Stack Overflow Blog
Stack Overflow Blog
Cyber Security Advisories - MS-ISAC
Cyber Security Advisories - MS-ISAC
The GitHub Blog
The GitHub Blog
A
About on SuperTechFans
Recent Announcements
Recent Announcements
L
LangChain Blog
Microsoft Azure Blog
Microsoft Azure Blog
小众软件
小众软件
J
Java Code Geeks
博客园_首页
Jina AI
Jina AI
美团技术团队
H
Help Net Security
MyScale Blog
MyScale Blog
Engineering at Meta
Engineering at Meta
奇客Solidot–传递最新科技情报
奇客Solidot–传递最新科技情报
人人都是产品经理
人人都是产品经理
Y
Y Combinator Blog
S
SegmentFault 最新的问题

... eeNews Europe

Molex Teramount deal targets co-packaged optics NVIDIA and ServiceNow extend AI governance from desktops to data centres Faraday Future launches Physical AI robotics institute with BIBS System Check: Should engineers learn analog? Decoupled by Design: How Gateworks and NXP are rethinking edge AI architecture NVIDIA and Corning partner on AI photonics expansion GCT taps satellite partner to speed 5G rollout Sodankylä supersite to support ESA Earth observation SiTime posts 88% revenue growth on AI infrastructure demand Infrared LEDs support in-cabin sensing for vehicle safety Anthropic compute deal taps SpaceXAI Colossus 1 Quantum Brilliance CEO Mark Luo on deployable quantum systems and the future of diamond-based computing SEMI Summit spotlights Europe’s chiplet and packaging push AI data center infrastructure drives Pennsylvania energy expansion NXP CoreRide gains Vector software support for SDV platforms Elektor Lab Talk covers Red Pitaya and reconfigurable test gear SEMI names Julie Rogers to lead ESD Alliance ASML CEO backs joint call for Europe tech competitiveness push FlexIC RFID inlays bring NFC to paper packaging ROHM targets smart rings with ultra-compact NFC wireless power chipset China silicon wafers push boosts Eswin capacity ESD Alliance outlook spotlights agentic AI in chip design AI robotics sales growth rises as Faraday Future expands into education Microchip expands dsPIC33A controllers for AI data center power sensiBel MEMS microphone heads to Silex production SEMI: Global silicon wafer shipments jump 13% on AI demand AI drives photonics innovation Advantech adds Intel Core Series 3 to edge AI systems NI CHESS enables software-driven RF channel emulation into aerospace testing Forsee Power battery system powers new electric fire pump
Diodes launches PCIe 7.0 clock generator
2026-05-20 · via ... eeNews Europe

Diodes launches PCIe 7.0 clock generator

New Products |

By Brian Tristam Williams




Diodes Incorporated has introduced the PI6CG33A06, a six-output, ultra-low-jitter clock generator for PCI Express 7.0 systems, while maintaining support for earlier PCIe generations.

The PCIe 7.0 clock generator is aimed at servers, networking equipment, high-performance computing systems and data centre platforms used in AI infrastructure. It was announced at the PCI-SIG Developers Conference in Santa Clara.

PCIe 7.0 clock generator for AI infrastructure

The PI6CG33A06 generates 25 MHz and 100 MHz reference clocks and achieves RMS jitter below 30 fs. That is below the 67 fs maximum requirement for the PCIe 7.0 specification and below the 80 fs level defined by Intel’s CK440Q specification.

At these data rates, the timing budget is tight. Diodes says the part provides a stable reference clock for 128.0 GT/s PCIe links, targeting 800G and 1.6T networking systems as well as advanced AI accelerators. As previously reported by eeNews Europe when PCIe 8.0 was outlined for AI infrastructure, the PCIe roadmap continues to push both bandwidth and signal-integrity requirements upwards.

Integrated termination reduces board complexity

The PI6CG33A06 uses Diodes’ low-power, high-speed current-steering logic technology with integrated termination. The company says this cuts clock-related power consumption by at least 50% compared with traditional HCSL implementations.

The integrated termination also removes the need for up to 24 external resistors. That reduces the bill of materials and simplifies PCB layout, while freeing board area in dense server designs where power delivery, memory placement and cooling already compete for space.

Each of the six outputs has an individual output-enable pin, allowing designers to shut down or manage outputs independently. The device supports Intel CK440Q-Lite specifications, so it can be used in existing server clock architectures while improving timing margin.

Package and availability

The PCIe 7.0 clock generator is supplied in a 40-pin, 5 mm x 5 mm VQFN package. Diodes lists pricing from $2.80 in 3,000-piece quantities.

If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :

   eeNews on Google News


Linked Articles