什么是cache
To minimize the quantity of control information stored, the spatial locality property is used to group several locations together under the same tag. This logical block is commonly known as a cache line.
When data is loaded into a cache, access times for subsequent loads and stores are reduced, resulting in overall performance benefits. An access to information already in a cache is known as a cache hit, and other accesses are called cache misses.

在S32K1xx的RM中可以看到。

This device includes one 4 KB code cache to minimize the performance impact of memory access latencies. The code cache exists on the I/D bus, and there is no cache on the system bus.

Cache的主要作用是降低访问主存（一般size都比较大）时的延迟。尤其是我们访问硬盘时，如果速度过慢，特别影响性能。当然，硬盘不是主存，这是另外一个话题。

Cache的存在对于用户是不可见的，只有的极少量的场合软件才需要去控制它。

对于一些嵌入式系统，我们似乎对这种性能的优化要小心。但是这种性能的优化导致的时间的不确定性能够以其他方式去解决。

WT = Write through, no write allocate.

WBWA = Write back, write allocate.

Write-allocate (WA)
In a write-allocate cache, a cache miss on storing data causes a cache line to be allocated into the cache.
在这种类型的cache（物理实体）中，发生了一个cache miss的事件，会导致 一块 logical block（也就是cache line）被分配。

Write-back (WB)
In a write-back cache, data is only written to main memory when it is forced out of the cache on line replacement following a cache miss. Otherwise, writes by the processor only update the cache. This is also known as copyback.

英语阅读理解：line replacement following a cache miss， 意思是cache miss发生之后会 line replacement。
cache miss followed by line replacement.

Write-through (WT) In a write-through cache, data is written to main memory at the same time as the cache is updated.
写的时候同步写入到主存。

Wikipedia中的词条中指出，TLB也是一种cache。
Other types of caches exist (that are not counted towards the "cache size" of the most important caches mentioned above), such as the translation lookaside buffer (TLB) which is part of the memory management unit (MMU) which most CPUs have.

所以，很多概念容易混淆。

参考资料：

https://en.wikipedia.org/wiki/CPU_cache

《Cortex-M0 Devices Generic User Guide》2009 ARM Limited.