推荐订阅源

要求检测3个字节的数据流，每个时钟收到一个字节，首字节的bit[3]是1就是起始字节，做数据流的边界判断，收到有效的3字节，输出一个时钟长度的标记信号done。

module top_module(
input clk,
input [7:0] in,
input reset, // Synchronous reset
output done); //
parameter BYTE1=2'h0,BYTE2=2'h1,BYTE3=2'h2,DONE=2'h3;
reg [1:0]state,next_state;
// State transition logic (combinational)
always @(*)
begin
case(state)
BYTE1:next_state=in[3]?BYTE2:BYTE1;
BYTE2:next_state=BYTE3;
BYTE3:next_state=DONE;
DONE:next_state=in[3]?BYTE2:BYTE1;
default:next_state=BYTE1;
endcase
end
// State flip-flops (sequential)
always @(posedge clk)
begin
if(reset)
state<=BYTE1;
else
state<=next_state;
end
// Output logic
assign done=state==DONE;
endmodule