INFRA

BoolSi raises $6M to compile ordinary code into custom chips

Chip-design startup BoolSi Inc. today announced it has raised $6 million in seed funding to build a compiler that turns ordinary software into custom hardware, doing away with the years of digital-logic training that chip design has always demanded.

Co-founder and Chief Executive Mihailo Isakov built BoolSi to aim at FPGAs, the field-programmable gate arrays that can be reconfigured after manufacturing and dropped in next to a central processing unit. The workflow is simple on the user’s end. A developer points the compiler at a slow spot in a program written in C, C++ or another high-level language and BoolSi returns a custom circuit and a driver.

The company says that takes minutes. Doing the same work by hand takes months.

Custom hardware can run fixed workloads far faster than a general-purpose processor. It spreads the computation across dedicated gates and wires that all run at once, which avoids the fetch-decode-execute overhead a CPU pays on every instruction. The tradeoff has always been difficulty.

Designing chips is closer to watchmaking than to programming, with millions of subcircuits that have to coordinate precisely. Open-source resources are thin and the cost of entry runs into years. Most software engineers never get a path into hardware, even when their applications would benefit from it.

BoolSi reframes the problem as learning what a program does, not translating how it is written. The company trains machine-learning models that converge into fully digital circuits, using the source program itself as a synthetic data generator. A fuzzer explores the input space and turns every run into an exactly labeled training example, which the company says makes 100% accuracy both achievable and required. For verification, BoolSi trains several independent models in parallel and formally checks them against one another.

The company makes the case with one benchmark, a regex routine that scans text for email addresses. Compiled with gcc -O3, the routine took 2.66 milliseconds on an ARM Cortex-A9 processor. A single BoolSi hardware agent did it in 0.325 milliseconds. That is about eight times faster. Eight agents running together finished in 0.042 milliseconds, 63 times quicker than the CPU.

BoolSi pitches the work against existing high-level synthesis tools such as Vivado HLS, Catapult and Bambu. It argues those tools made hardware engineers more productive but never opened the field to software developers.

The startup is aiming first at embedded developers in robotics, where jobs such as motor-control loops, sensor fusion and model-predictive control hammer general-purpose processors over and over. A private beta is set to open in the third quarter. BoolSi is starting with FPGAs because they let developers ship right away, and it expects the underlying toolchain to extend to custom ASIC chips as workloads settle.

The seed round was led by Fine Structure Ventures, an F-Prime fund, with Pillar VC, Fifth Quarter Ventures and Coalition Ventures participating.

Photo: BoolSi