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eess.SP updates on arXiv.org

ECG-biometrics-bench: A Unified Framework for Reproducible Benchmarking of ECG Biometrics Physiology-Aware Masked Cross-Modal Reconstruction for Biosignal Representation Learning Towards Improving Speaker Distance Estimation through Generative Impulse Response Augmentation Federated Learning with Hypergradient-based Online Update of Aggregation Weights Soft Graph Diffusion Transformer for MIMO Detection SPLICE: Latent Diffusion over JEPA Embeddings for Conformal Time-Series Inpainting Sequential Inference for Gaussian Processes: A Signal Processing Perspective Statistical Channel Fingerprint Construction for Massive MIMO: A Unified Tensor Learning Framework Recent Advances in mm-Wave and Sub-THz/THz Oscillators for FutureG Technologies Cross-Subject Generalization for EEG Decoding: A Survey of Deep Learning Methods Super-resolution Multi-signal Direction-of-Arrival Estimation by Hankel-structured Sensing and Decomposition Hankel and Toeplitz Rank-1 Decomposition of Arbitrary Matrices with Applications to Signal Direction-of-Arrival Estimation Adaptive Transform Coding for Semantic Compression EdgeSpike: Spiking Neural Networks for Low-Power Autonomous Sensing in Edge IoT Architectures Sparse Graph Learning from Sparse Data via Fiedler Number Maximization A Deep Learning Model for Battery State Prediction towards Intelligent Energy Management Transfer Learning for Tonal Noise Prediction in VRF Units Using Thermodynamic and Vibration Signals EVT-Based Generative AI for Tail-Aware Channel Estimation Monitoring exposure-length variations in submarine power cables using distributed fiber-optic sensing BandRouteNet: An Adaptive Band Routing Neural Network for EEG Artifact Removal Phase-Separated Complex Hilbert PCA on Markerless 3D Pose Estimation Data: A Global Phase Network and Its Extension to a Continuous Field on the Body Surface Selective Correlation Based Knowledge Distillation for Ground Reaction Force Estimation Deep Learning-Enabled Dissolved Oxygen Sensing in Biofouling Environments for Ocean Monitoring Speech Enhancement Based on Drifting Models Robust and Clinically Reliable EEG Biomarkers: A Cross Population Framework for Generalizable Parkinson's Disease Detection An AI-Based Supervisory Measurement Integrity Validation Layer for Cyber-Resilient AC/DC Protection in Inverter-Based Microgrids Explainable AI in Speaker Recognition -- Making Latent Representations Understandable Time-Localized Parametric Decomposition of Respiratory Airflow for Sub-Breath Analysis NAKUL-Med: Spectral-Graph State Space Models with Dynamics Kernels for Medical Signals An Algorithm for On-Sensor Agnostic Detection of Changes in Human Activity for Ultra-Low-Power Applications
Cost-effective Energy Monitoring of a Zynq-based Real-tim...
2019-03-22 · via eess.SP updates on arXiv.org

The ongoing integration of fine-grained power management features already established in CPU-driven Systems-on-Chip (SoCs) enables both traditional Field Programmable Gate Arrays (FPGAs) and, more recently, hybrid Programmable SoCs (pSoCs) to reach more energy-sensitive application domains (such as, e.g., automotive and robotics). By combining a fixed-function multi-core SoC with flexible, configurable FPGA fabric, the latter can be used to realize heterogeneous Real-time Systems (RTSs) commonly implementing complex application-specific architectures with high computation and communication (I/O) densities. Their dynamic changes in workload, currently active power saving features and thus power consumption require precise voltage and current sensing on all relevant supply rails to enable dependable evaluation of the various power management techniques. In this paper, we propose a low-cost 18-channel 16-bit-resolution measurement (sub-)system capable of 200 kSPS (kilo-samples per second) for instrumentation of current pSoC development boards. To this end, we join simultaneously sampling analog-to-digital converters (ADCs) and analog voltage/current sensing circuitry with a Cortex M7 microcontroller using an SD card for storage. In addition, we propose to include crucial I/O components such as Ethernet PHYs into the power monitoring to gain a holistic view on the RTS's temporal behavior covering not only computation on FPGA and CPUs, but also communication in terms of, e.g., reception of sensor values and transmission of actuation signals. We present an FMC-sized implementation of our measurement system combined with two Gigabit Ethernet PHYs and one HDMI input. Paired with Xilinx' ZC702 development board, we are able to synchronously acquire power traces of a Zynq pSoC and the two PHYs precise enough to identify individual Ethernet frames.