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cs.CR updates on arXiv.org

Agentic Vulnerability Reasoning on Windows COM Binaries From Beats to Breaches:How Offensive AI Infers Sensitive User Information from Playlists Undetectable Backdoors in Model Parameters: Hiding Sparse Secrets in High Dimensions When Embedding-Based Defenses Fail: Rethinking Safety in LLM-Based Multi-Agent Systems Token-Efficient Change Detection in LLM APIs Selfie-Capture Dynamics as an Auxiliary Signal Against Deepfakes and Injection Attacks for Mobile Identity Verification Trident: Improving Malware Detection with LLMs and Behavioral Features When Alignment Isn't Enough: Response-Path Attacks on LLM Agents RefusalGuard: Geometry-Preserving Fine-Tuning for Safety in LLMs Checkerboard: A Simple, Effective, Efficient and Learning-free Clean Label Backdoor Attack with Low Poisoning Budget Block-wise Codeword Embedding for Reliable Multi-bit Text Watermarking Secret Stealing Attacks on Local LLM Fine-Tuning through Supply-Chain Model Code Backdoors Enhancing Linux Privilege Escalation Attack Capabilities of Local LLM Agents Defusing the Trigger: Plug-and-Play Defense for Backdoored LLMs via Tail-Risk Intrinsic Geometric Smoothing Evaluating Jailbreaking Vulnerabilities in LLMs Deployed as Assistants for Smart Grid Operations: A Benchmark Against NERC Standards Behavioral Canaries: Auditing Private Retrieved Context Usage in RL Fine-Tuning FlexServe: A Fast and Secure LLM Serving System for Mobile Devices with Flexible Resource Isolation Breaking MCP with Function Hijacking Attacks: Novel Threats for Function Calling and Agentic Models Text Steganography with Dynamic Codebook and Multimodal Large Language Model An AI Agent Execution Environment to Safeguard User Data TwoHamsters: Benchmarking Multi-Concept Compositional Unsafety in Text-to-Image Models Fundamental Limitations of Favorable Privacy-Utility Guarantees for DP-SGD Symbolic Guardrails for Domain-Specific Agents: Stronger Safety and Security Guarantees Without Sacrificing Utility Hardening x402: PII-Safe Agentic Payments via Pre-Execution Metadata Filtering QShield: Securing Neural Networks Against Adversarial Attacks using Quantum Circuits Hijacking Text Heritage: Hiding the Human Signature through Homoglyphic Substitution Like a Hammer, It Can Build, It Can Break: Large Language Model Uses, Perceptions, and Adoption in Cybersecurity Operations on Reddit Private Seeds, Public LLMs: Realistic and Privacy-Preserving Synthetic Data Generation One Word at a Time: Incremental Completion Decomposition Breaks LLM Safety Measuring and Exploiting Contextual Bias in LLM-Assisted Security Code Review
Logical Maneuvers: Detecting and Mitigating Adversarial H...
Fatemeh Khojasteh Dana, Saleh Khalaj Monfared, Shahin Tajik · 2025-01-24 · via cs.CR updates on arXiv.org

Satellites are highly vulnerable to adversarial glitches or high-energy radiation in space, which could cause faults on the onboard computer. Various radiation- and fault-tolerant methods, such as error correction codes (ECC) and redundancy-based approaches, have been explored over the last decades to mitigate temporary soft errors on software and hardware. However, conventional ECC methods fail to deal with hard errors or permanent faults in the hardware components. This work introduces a detection- and response-based countermeasure to deal with partially damaged processor chips. It recovers the processor chip from permanent faults and enables continuous operation with available undamaged resources on the chip. We incorporate digitally-compatible delay-based sensors on the target processor's chip to reliably detect the incoming radiation or glitching attempts on the physical fabric of the chip, even before a fault occurs. Upon detecting a fault in one or more components of the processor's arithmetic logic unit (ALU), our countermeasure employs adaptive software recompilations to resynthesize and substitute the affected instructions with instructions of still functioning components to accomplish the task. Furthermore, if the fault is more widespread and prevents the correct operation of the entire processor, our approach deploys adaptive hardware partial reconfigurations to replace and reroute the failed components to undamaged locations of the chip. To validate our claims, we deploy a high-energy near-infrared (NIR) laser beam on a RISC-V processor implemented on a 28~nm FPGA to emulate radiation and even hard errors by partially damaging the FPGA fabric. We demonstrate that our sensor can confidently detect the radiation and trigger the processor testing and fault recovery mechanisms. Finally, we discuss the overhead imposed by our countermeasure.