I’ve attended every GTC since 2011, and I can safely say this year’s show in San Jose featured the most architecturally complete keynote Jensen Huang has ever delivered. But between the Vera Rubin racks and the Groq LPU integration, I kept coming back to a conversation I had earlier in the week with a company most people haven’t heard of yet: Velaura AI.
For more than two years, I’ve been saying that power, not compute capability, is becoming the binding constraint on AI scaling. The International Energy Agency projects that annual datacenter electricity demand will more than double — to roughly 945 TWh — by 2030, more than what Japan consumes today. AI is the primary driver.
As I wrote shortly after meeting Velaura at GTC, the last three years in AI silicon have been all about chasing higher TFLOPS. That era is ending. The real test for chip developers over the next three years will be how much they can reduce power consumption per TFLOP. Velaura’s Titan Core platform is one of the more interesting approaches I’ve seen and, unlike most AI silicon startups, it already has tens of millions of production chips in the field.
On March 24, Velaura AI (formerly Auradine) unveiled Titan Core, a silicon design and IP platform targeting power efficiency for AI accelerators. The company claims it can deliver up to 2x lower overall chip power for GPUs and custom AI processors — directly addressing the power-consumption bottleneck the IEA is warning about. CEO Rajiv Khemani put it directly: “The future of AI will be defined by who can deliver the most meaningful performance within real-world power limits.”
Velaura isn’t building its own accelerator, which I think is what makes the business model interesting. It takes a customer’s existing chip design for the power-hungry math blocks, applies proprietary low-voltage design libraries and custom design tool flows, and delivers an optimized physical layout. No software changes, no chip redesign, but the customer gets a drop-in replacement for the most power-hungry part of the chip. Think of it as a specialized power-optimization service backed by years of silicon IP.
As my colleague Matt Kimball wrote in his analysis of transistor leadership in the sub-2nm world, “The defining constraint in modern computing is no longer demand for compute. It is the ability to deliver exponentially more compute within a fixed power, thermal, and physical envelope.” Datacenters are running into walls created by physics. You can’t even cool a datacenter if you can’t power it, and you can’t power it if the grid won’t deliver enough electricity.
Consider the numbers. As Kimball noted in his research on datacenter sustainability, the next-generation NVIDIA Rubin-series GPUs will draw between 1,400 and 1,800 watts per chip. AMD’s MI400 series is in the same range. At the rack level, power densities could approach 380 kilowatts. The thirst for power is forcing the industry to disaggregate AI workloads into specialized components: Consider the recent announcements about NVIDIA’s Vera CPX for pre-fill, NVIDIA’s use of Groq’s LPU for decode, and AMD’s low-power GPU work with Meta. Every one of these moves seeks to resolve the same constraint.
Inside every AI accelerator, power consumption is spread unevenly. Depending on the workload, roughly 40 to 70% of total chip power goes to the matrix math that underpins AI training and inference. These are massive arrays of circuits performing billions of multiply-and-add calculations per second. When a large language model processes a prompt or an image model generates a picture, this is where the heavy lifting happens. Everything else on the chip — memory, I/O, control logic — consumes the rest. So if you want to make a real dent in power, the math blocks are the target.
Velaura’s approach exploits a basic property of chip physics, which is that power consumption rises exponentially with voltage. Cut the operating voltage in half and you don’t just halve the power demand, you cut it to roughly one-quarter. Most AI chips today run their math blocks at around 700 to 800 millivolts. Velaura runs them significantly lower than that.
But three problems arise if you try to simply turn down the voltage when you’re working with advanced chip manufacturing processes at 3nm or 2nm nodes. First, the chip’s clock speed drops because at lower voltages transistors switch slower, so you lose performance. Second, the chip becomes more vulnerable to random errors caused by stray particles flipping circuit states. Third, more chips fail testing — and manufacturing yield thus suffers — because the tiny process variations in every wafer have a bigger impact at low voltages. Solving all three challenges simultaneously to keep speed up, errors down, and yield high while running at significantly reduced voltages is what makes this problem genuinely hard. It requires custom circuit designs, purpose-built design tool flows, and error-correction techniques baked into the silicon.
This is where Velaura brings its design history to bear. The company spent more than four years perfecting these techniques in the high-volume production of Bitcoin mining chips. (Yes, the crypto pedigree raises eyebrows, but the silicon engineering transfers directly regardless of the end application.) At their core, mining chips are massive arrays for running structured math operations, and they’re structurally similar to the matrix engines inside AI accelerators. Velaura claims its service approach delivers a 3x to 4x power reduction in the math blocks while maintaining the same performance. At the full chip level, that translates to the up-to-2x overall reduction the company is advertising.
It’s important to note that this technology is specific to throughput-oriented, highly replicated blocks. It doesn’t apply to CPUs, caches, or latency-sensitive logic. But that’s a strength, not a weakness, because Velaura targets the biggest power hog on an AI accelerator without requiring the customer to touch anything else.
On a per-chip basis, the math is straightforward. A 250- to 500-watt reduction on a 1,000-watt accelerator, running continuously at $0.10 per kilowatt-hour, saves $650 to $1,300 per chip over three years. Across 100,000 accelerators, that’s $65 million to $130 million in direct electricity savings. These are significant numbers, but they don’t tell the whole story.
The bigger value is capacity. In power-constrained datacenters, every watt saved at the silicon level can be redeployed as additional compute. You can pack more accelerators into the same rack, extend existing power infrastructure, or defer building a new facility. When construction costs are running into the billions and grid connection timelines are stretching out to years — which is the world we live in — doing more within an existing power envelope is worth multiples of the energy savings. Factor in typical cooling overhead, roughly 50 cents of infrastructure power for every dollar of IT power, and the cascade effect gets even larger.
I’ve been covering AI silicon startups for many years and I’ve scrutinized their performance claims since 2020. I can tell you that the landscape is full of impressive simulation results that don’t survive contact with real manufacturing. What separates Velaura is its more than 30 million ASICs, shipped on TSMC’s leading-edge process nodes, that are running in production today. That’s not a prototype or a claim on slide 4 of a pitch deck. (I’ve sat through enough AI chip startup pitches over the years to know the difference between simulation results and real silicon performance.)
Velaura’s team isn’t a group of first-timers, either. Founders and leadership hail from Qualcomm, Marvell, NVIDIA, Intel, Apple, and Google. Board member — and chip-industry legend — Lip-Bu Tan is Intel’s CEO. The company holds 90 patents (32 granted) and has $275 million in venture backing. As I said in my quote for its press release, “That production track record at 3nm is what separates this from a whiteboard exercise.”
I don’t want to oversell this. The power-reduction claims are based on internal analysis and customer engagements, not independent benchmarks. Until a third party confirms the results under realistic conditions, these remain vendor claims — credible ones, but vendor claims nonetheless.
Hyperscaler adoption is also a long-cycle decision. The press release says that Velaura has “ongoing engagements with several leading hyperscaler XPU partners.” Engagements aren’t design wins. Getting a hyperscaler to hand over its most sensitive chip design files requires extraordinary trust. That’s a real go-to-market hurdle.
Competitors aren’t standing still, either. Every major accelerator vendor has internal teams working hard to reduce power consumption. And EDA companies Synopsys and Cadence are investing in low-voltage tools. Velaura argues its two- to three-year head start can’t be replicated quickly, and the engineering complexity supports that. However, that moat could erode if incumbents prioritize it, and the company itself is in transition as it pivots from Bitcoin-mining chip revenue to AI IP licensing, a fundamentally different business.
I’m cautiously positive on the Titan Core platform. Velaura’s production record is real, the physics argument is sound, the team has depth, and the timing is right. Every hyperscaler and AI chip vendor is confronting power constraints — constraints with real teeth — that didn’t exist three years ago.
But I condition my optimism on independent validation and at least one converted design win. I’ve seen too many promising silicon technologies fail to cross the gap between “impressive engineering” and “shipping in someone else’s product at scale.” That gap is where most startups die.
The future of AI compute won’t be measured only in TFLOPS. It will be measured in watts per TFLOP, dollars per watt, and compute capacity per megawatt of grid power. Whoever solves the efficiency equation at the silicon level will have an outsized impact on how fast AI scales from here. I’m watching this one closely.
(Note: I am an investor in Velaura AI.)
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