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博客园 - 岁月长河

emacs. verilog mode guide, example Powershell cmdlet 正则表达式篇 之三(BRE和ERE区别)及ELISP ISP architecture considering AHB 总线笔记 English Dictionary site for ODE and OALD vmic environment makefile the diference between include and import windows 工具命令 cmd python namespace shell cmd args ROE, ROC IP 链接及常用软件 vim 分屏 and command usages vim autocmd 记录 consonant combination
irun vcs option
岁月长河 · 2019-01-08 · via 博客园 - 岁月长河

irun:

-input dump.tcl

-sv compile by sv source 

---恢复内容结束---

+acess+wrc

-timescale

dump.tcl

fsdbDumpfile “”

fsdbDumpvars [depth] [var]

fsdbDumpflush;

$fsdbAutoSwitchDumpfile(300,"./test_top.fsdb",40);

$fsdbDumpvarsToFile("dump.list");

//dump.tcl for vcs

fsdbDumpfile "filename"

fsdbDumpvars 

run

exit

run

fsdbDumpMDA

vcs 

-y  search library directory 

+libext+extention

-v search library file

For TCL 

set env(MY_VAR)  Modification.

set  var                $env(MY_VAR)  read the env var

For synthesis

muticycle 

1: -end   indicate launch point is fixed, and move clock counts on the sampling clock by clock; used to fast clock sampling the slow clock

set_multicycle_path -setup 3 -end -from clk1 -to clk2

set_multicycle_path -hold   2 -start -from clk1 -to clk2

2: -start indicate sampling point fixed, and move clock counts on the driving clock by clock; used to slow clock sampling the fast clock

set_multicycle_path -setup 3 -start -from clk1 -to clk2
set_multicycle_path -hold   2 -start -from clk1 -to clk2

https://www.cnblogs.com/IClearner/p/6618992.html

 

 

vdCov -covdir mergedir_new.vdb/ &

urg -dir ./simv.vdb -dbname mergedir/merged

gate_unit

0.05472 7nm

0.145152 14nm