推荐订阅源

把检测到成功收到的串行数据流中的8位数据位输出。

module top_module(
input clk,
input in,
input reset, // Synchronous reset
output [7:0] out_byte,
output done
); //
reg [9:0]data_in;
parameter IDLE=0,START=1,BIT0=2,BIT1=3,BIT2=4,BIT3=5,BIT4=6,
BIT5=7,BIT6=8,BIT7=9,STOP=10,ERROR=11;
reg[3:0]state,next_state;
// Use FSM from Fsm_serial
always @(*)
case(state)
IDLE:next_state=in?IDLE:START;
START:next_state=BIT0;
BIT0:next_state=BIT1;
BIT1:next_state=BIT2;
BIT2:next_state=BIT3;
BIT3:next_state=BIT4;
BIT4:next_state=BIT5;
BIT5:next_state=BIT6;
BIT6:next_state=BIT7;
BIT7:next_state=in?STOP:ERROR;
STOP:next_state=in?IDLE:START;
ERROR:next_state=in?IDLE:ERROR;
default:next_state=IDLE;
endcase

always @(posedge clk)
if(reset)
state<=IDLE;
else
state<=next_state;
assign done=state==STOP;

// New: Datapath to latch input bits.
always @(posedge clk)
if(reset)
data_in<=10'h0;
else
data_in<={in,data_in[9:1]};

assign out_byte=(state==STOP)?data_in[8:1]:10'hx;
endmodule