TSMC's chip-on-wafer-on-substrate (CoWoS) packaging technology has become the de facto standard packaging method for advanced AI and HPC processors that use HBM memory, thanks to TSMC's aggressive development of the technology. Unlike lateral 2.5D CoWoS, TSMC's vertically integrated System on Integrated Chips (SoIC) technology with 3D interconnects has not been adopted as widely. However, now that the company has overcome the first generation's constraints, it will aggressively develop this technology in the coming years, as the company revealed at its recent North American Technology Symposium.
