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Latest from Tom's Hardware in Semiconductors

Post-silicon era gets closer as industry giants crack the 2D transistor scaling bottleneck with breakthrough tech — imec, ASML, and TSMC fab complementary 2D-material transistors at 50nm pitch on a 300mm wafer Intel Intel’s performance-enhanced 18A-P process enters risk production — drop-in 18A upgrade promises 9% performance improvement at iso-power, cuts thermal resistance by 40% Chinese fab SMIC TSMC says panel packaging won Analyzing TSMC's fab expansion roadmap — multi-fab N2 ramp, CoWoS, SoIC, and uncorking bottlenecks Chinese startup claims photonic chip production without DUV lithography, says nanoimprint process cuts costs by 90%… ASML becomes Europe's most valuable company ever as analysts bet on higher EUV output — its market cap hit… TSMC CEO C.C. Wei says, ‘It will be a long time before we can meet customer demand’ — tells shareholders that he will keep prices stable, refrain from implementing price hikes Samsung shows first HBM5 mockup with Heat Path Block cooling — thermal race with SK hynix shaping up Seven hospitalized after toxic gas fire at SK hynix advanced memory plant — Cheongju 4th campus incident today led… TikTok owner ByteDance is reportedly developing its own custom AI CPUs — company looks to ease China's… Trailing-edge foundry roadmaps for GlobalFoundries, UMC, and SMIC — mature node chipmakers each pursue differing… Chinese university builds 3D chip design tool tailored to Huawei's ‘LogicFolding’ architecture — 3D design delivers increased performance and better thermal management China adds homegrown AI chips to 'secure and reliable' procurement list for the first time — nine options added as move away from Nvidia continues SK hynix unveils 'iHBM' thermal architecture that cools AI memory at the source — integrated cooling elements inside HBM interface cut thermal resistance by 30%, target next-gen HBM5 accelerators and dense AI data centers Imec builds world's first High-NA EUV-fabricated quantum dot qubit device — breakthrough could pull quantum computing onto the same manufacturing roadmap as next-gen AI processors, compressing timelines Huawei claims sanctions-busting breakthrough with 1.4nm-class chips by 2031, claims 55% higher transistor density — firm claims new LogicFolding chip architecture can bypass EUV restrictions, introduces 'Tau Scaling Law' to replace Moore's Law Samsung's $400,000 payout for memory workers sparks revolt as other divisions get only $4,000, fueling intentional production slowdowns — internal resentment disrupts packaging operations, major AI chip project decisions to a complete halt The custom AI ASIC state of play (May 2026) — Broadcom deals, Google TPUs, Meta MTIA & beyond AMD begins production ramp of 256-core EPYC Venice — first 2nm HPC chip claims 70% performance leap Intel kicks off development on next-decade 10A and 7A process technologies — 14A node remains on track for… SMIC founder and AMEC CEO urge Chinese fabs to test domestic chipmaking tools on active production lines — equipment makers post record revenue but falling margins Russia’s Mikron is selling framed test wafers with up to 120,000 processors as souvenirs — 12 designs, priced around $170 each, sold alongside $2 vials of cleanroom air Trump calls $14 billion Taiwan arms deal a 'negotiating chip' with China after Xi said Taiwan issue could lead to 'clashes and even conflicts' — Trump says 'Taiwan would be very smart to cool it a little bit' Leading-edge foundry roadmaps for TSMC, Intel and Samsung — outlining the path to 1.4nm nodes and beyond TSMC allocates $20 billion to Arizona expansion — project faces water and labor shortages, complicated by visa… NASA partners with Microchip to build next-generation spaceflight chips with 100x the power of current offerings — chip designed to withstand radiation for extended missions on the Moon and Mars Intel, SK hynix shares surge following reports of chip packaging partnership — SK is said to be testing… Apple reportedly strikes deal for Intel to make some of its chips — two tech giants reached a preliminary…
Ambitious semiconductor enthusiast builds DIY 'class 100 ...
Mark Tyson · 2026-03-11 · via Latest from Tom's Hardware in Semiconductors

Semiconductor facilities are the super-high-tech cradles of all the tech we cherish, and an essential component of one of these ‘fabs’ is the cleanroom environment. However, a TechTuber called Dr. Semiconductor has successfully created a ‘Class 100 cleanroom’ (ISO 5) in his garden shed. Actually, he’s done quite a bit more than just make an empty cleanroom, with a set of interesting but compact chip tools already installed.

There’s a Class 100 semiconductor cleanroom inside this backyard shed. - YouTube There’s a Class 100 semiconductor cleanroom inside this backyard shed. - YouTube

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As the good doctor says, all the RAM, CPUs, and GPUs that PC enthusiasts covet rely on clean room facilities. Tech giants like Intel, Samsung, and TSMC will spend billions of dollars constructing their cleanroom facilities. There, they will fabricate chips “inside cleanrooms thousands of times cleaner than a hospital operating room.”

This environment is essential, as a single speck of dust can ruin a whole chip or wafer. A speck of dust is like a boulder on a landscape built from the tiniest, intricate structures. Dust can also contaminate optics and other sensitive tools in the semiconductor process chain. Despite Elon Musk's claims, smoking cigars and eating burgers in a cleanroom would definitely be regarded as a lapse in decorum, if not worse.

Dr. Semiconductor began his shed transformation by sealing the environment. We see various steps in reinforcing the internal shed structure. The enthusiast stresses that airflow and positive pressure are the true keys to an effective cleanroom. And the same positive-pressure methodology can help keep a PC's interior clean.

Once the TechTuber was satisfied with his sealing and filtration systems, he borrowed a particle counter. The instrument confirmed that he had achieved a Class 100 cleanroom standard in terms of particle count.

DIY cleanroom in a shed

(Image credit: Dr. Semiconductor )

Entering the finished semiconductor shed, you first enter a gowning area, which will be familiar to anyone who has been to a commercial or academic facility. Dr. Semiconductor’s tour shows that as we step into this area, there is a power management area which leverages grid and solar power, shelving with clean room suits, gloves, and chemical supplies.

In the video, after suiting up and crossing into the cleanroom, we get a guided tour from its creator. “It’s compact, but every inch is intentional,” says the good doctor. “It has everything needed in order to make this a fully functioning semiconductor R&D space.”

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Indeed, the tiny cleanroom isn’t just a sterile empty space; it contains some chipmaking tools. Dr. Semiconductor shows us his plasma etcher, vacuum furnace, and custom software-driven lithography machine to the left of the entrance. On the right side, there is a fume hood for chemical processing and spin coating (3D printed spin coater shown). A sample cleaner with a robot arm, some clear workspace, and a thin film deposition system are also present.

DIY cleanroom in a shed

(Image credit: Dr. Semiconductor )

The video ends there, but Dr. Semiconductor teases that he is looking forward to sharing details of the whole setup, “from the engineering tool sets, to how it all works, and all the crazy things that can be built — from circuits to sensors, to LEDs, and just so much more.”

Those particularly interested in hobbyist chipmaking might want to follow in Dr. Semi’s footsteps, or just see what is possible in a shed in 2026. In either case, it wouldn’t hurt to subscribe to the channel.

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Mark Tyson is a news editor at Tom's Hardware. He enjoys covering the full breadth of PC tech; from business and semiconductor design to products approaching the edge of reason.