All three leading-edge foundries — Intel Foundry, Samsung Foundry, and TSMC — have initiated mass production of chips using 2nm-class process technology. Samsung was the first one to start production using its SF2 node (though it could be argued that this is a rebadged SF3P) around mid-2025, Intel followed suit with its 18A node in November (albeit at development lines in Oregon, not production lines in Arizona), and TSMC initiated high-volume manufacturing using its N2 process at two volume fabs in Taiwan in December. We outline what's next for these three leading-edge foundries.
The current state of the market
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| Row 0 - Cell 0 | 18A vs 3 | 18A vs 20A | 18A-P vs 18A | 14A vs 18A | 14A-E vs 14A |
Power | 15% perf. per watt | 10% perf. per watt | 18% | 25% - 35% | lower |
Performance | 15% perf. per watt | 10% perf. per watt | 9% | 15% - 20% | higher |
Density* | 1.3X | slightly higher | - | 1.3X | higher |
Transistor | RibbonFET GAA | RibbonFET GAA | RibbonFET GAA | 2nd Gen RibbonFET GAA | 2nd Gen RibbonFET GAA |
Power Delivery | PowerVia BSPDN | PowerVia BSPDN | PowerVia BSPDN | PowerDirect BSPDN | PowerDirect BSPDN |
High Volume Manufacturing | H2 2025 | H2 2025 | 2027 (?) | 2028 (?) | 2029 (?) |
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| Row 0 - Cell 0 | A16 vs N2P | N2X vs N2P | N2U vs N2P | A14 vs N2 | A13 vs A14 | A12 vs A16 |
Power | -15% ~ -20% | lower | 8% - 10% | -25% ~ -30% | ? | lower |
Performance | 8% - 10% | 10% | 3% - 4% | 10% - 15% | ? | higher |
Chip Density* | 1.07x - 1.10x | ? | ? | 1.2x | ? | denser |
Logic Density | ? | ? | 1.02X - 1.03X | 1.23x | 1.06X | denser |
Transistor | GAA | GAA | GAA | 2nd Gen GAA | 2nd Gen GAA | 2nd Gen GAA |
Power Delivery | SPR | Front-side w/ SHPMIM (?) | Front-side w/ SHPMIM (?) | Front-side w/ SHPMIM (?) | Front-side w/ SHPMIM (?) | SPR |
High Volume Manufacturing | 2027 | 2027 | 2027 | 2028 | 2029 | 2029 |