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Latest from Tom's Hardware in Semiconductors

Post-silicon era gets closer as industry giants crack the 2D transistor scaling bottleneck with breakthrough tech — imec, ASML, and TSMC fab complementary 2D-material transistors at 50nm pitch on a 300mm wafer Intel Intel’s performance-enhanced 18A-P process enters risk production — drop-in 18A upgrade promises 9% performance improvement at iso-power, cuts thermal resistance by 40% Chinese fab SMIC TSMC says panel packaging won Analyzing TSMC's fab expansion roadmap — multi-fab N2 ramp, CoWoS, SoIC, and uncorking bottlenecks Chinese startup claims photonic chip production without DUV lithography, says nanoimprint process cuts costs by 90%… ASML becomes Europe's most valuable company ever as analysts bet on higher EUV output — its market cap hit… TSMC CEO C.C. Wei says, ‘It will be a long time before we can meet customer demand’ — tells shareholders that he will keep prices stable, refrain from implementing price hikes Samsung shows first HBM5 mockup with Heat Path Block cooling — thermal race with SK hynix shaping up Seven hospitalized after toxic gas fire at SK hynix advanced memory plant — Cheongju 4th campus incident today led… TikTok owner ByteDance is reportedly developing its own custom AI CPUs — company looks to ease China's… Trailing-edge foundry roadmaps for GlobalFoundries, UMC, and SMIC — mature node chipmakers each pursue differing… Chinese university builds 3D chip design tool tailored to Huawei's ‘LogicFolding’ architecture — 3D design delivers increased performance and better thermal management China adds homegrown AI chips to 'secure and reliable' procurement list for the first time — nine options added as move away from Nvidia continues SK hynix unveils 'iHBM' thermal architecture that cools AI memory at the source — integrated cooling elements inside HBM interface cut thermal resistance by 30%, target next-gen HBM5 accelerators and dense AI data centers Imec builds world's first High-NA EUV-fabricated quantum dot qubit device — breakthrough could pull quantum computing onto the same manufacturing roadmap as next-gen AI processors, compressing timelines Huawei claims sanctions-busting breakthrough with 1.4nm-class chips by 2031, claims 55% higher transistor density — firm claims new LogicFolding chip architecture can bypass EUV restrictions, introduces 'Tau Scaling Law' to replace Moore's Law Samsung's $400,000 payout for memory workers sparks revolt as other divisions get only $4,000, fueling intentional production slowdowns — internal resentment disrupts packaging operations, major AI chip project decisions to a complete halt The custom AI ASIC state of play (May 2026) — Broadcom deals, Google TPUs, Meta MTIA & beyond AMD begins production ramp of 256-core EPYC Venice — first 2nm HPC chip claims 70% performance leap Intel kicks off development on next-decade 10A and 7A process technologies — 14A node remains on track for… SMIC founder and AMEC CEO urge Chinese fabs to test domestic chipmaking tools on active production lines — equipment makers post record revenue but falling margins Russia’s Mikron is selling framed test wafers with up to 120,000 processors as souvenirs — 12 designs, priced around $170 each, sold alongside $2 vials of cleanroom air Trump calls $14 billion Taiwan arms deal a 'negotiating chip' with China after Xi said Taiwan issue could lead to 'clashes and even conflicts' — Trump says 'Taiwan would be very smart to cool it a little bit' Leading-edge foundry roadmaps for TSMC, Intel and Samsung — outlining the path to 1.4nm nodes and beyond TSMC allocates $20 billion to Arizona expansion — project faces water and labor shortages, complicated by visa… NASA partners with Microchip to build next-generation spaceflight chips with 100x the power of current offerings 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said he sleeps 'with one eye open' ASML makes breakthrough in EUV chipmaking tech, plans to increase speed by 50% by 2030 — new 1,000-watt light source fires three lasers at 100,000 tin droplets every second The state of China's decade-long semiconductor push: still a decade behind, despite hundreds of billions spent and significant progress — examining the original 'Made in China 2025' initiative TSMC considers an additional $100 billion investment into Arizona fabs to bolster American chipmaking efforts — move would help TSMC's chips avoid tariffs due to local production Rapidus targets mass 2nm chip production in 2027, quadruples capacity ramp up — company plans to scale to 25,000… Tachyum forced to shutter R&D office due to unpaid rent, wages, and taxes — firm still claims forthcoming Prodigy chip will have a 21x performance leap on Nvidia Rubin Ultra Cadence embeds AI 'super agent' to assist engineers when designing EDA tools — company aims for ‘over a trillion transistors’ by 2030, with AI helping to debug and verify complex projects Memory hoarding and skyrocketing prices hit entry-level electronics demand, foundry orders — China's top chipmaker points to supply chain pressures squeezing out consumers U.S. lawmakers demand sales ban on chipmaking tools to China — bipartisan group targets ASML's Dutch exports of lithography machines used to create advanced chips Memory makers are set to earn $551 billion from the AI boom, twice as much as contract chip manufacturers — forecasts suggest that 2026 revenue will skyrocket thanks to data center demand
Imec's new post-exposure bake method speeds up EUV chipmaking tools, boosting production for the most advanced chips — 20% gain in photoresist improvement from increased oxygen concentration
Anton Shilov · 2026-02-27 · via Latest from Tom's Hardware in Semiconductors
Imec
A photograph of the BEFORCE tool, short for ‘Bake and EUV system with FTIR
and Outgas measurement for Resist evaluation in Controlled Environment’.
(Image credit: Imec)

Imec has demonstrated that the photo-speed of metal-oxide resist (MOR) can be improved significantly when oxygen concentration is raised beyond atmospheric levels during the EUV post-exposure bake (PEB) step. Faster photo-speed means the resist reaches target dimensions at a lower EUV dose, which directly improves EUV scanner throughput and reduces exposure cost. Gas composition in the PEB chamber has not been widely treated as an EUV optimization knob, which makes the announcement significant, but it remains to be seen whether this can be industrialized.

Go deeper with TH Premium: Chipmaking

Scientists from Imec discovered that raising oxygen levels from 21% (ambient air) to 50% during the EUV PEB step results in a 15% – 20% increase in photo-speed, which means that the metal-oxide resist can reach its target dimension at a lower EUV dose. Lower dose cuts exposure time, which in turn increases an EUV scanner's throughput per hour and can reduce the cost of EUV step per wafer and ultimately per chip, though do not expect the lowered exposure cost to have a significant impact on the cost of the final product. The improvement was confirmed for both experimental MOR formulations and commercially available MOR materials, according to Imec.

Metal-oxide resists have become leading candidates for advanced process technologies that rely on Low-NA EUV and eventually on High-NA EUV lithography as their high-resolution capability, lower line-edge roughness, and favorable dose-to-size characteristics outperform those of chemically amplified resists (CARs), which are widely used today. The high resolution and reduced LER directly translate into better pattern transfer capability for the smallest features of critical layers set to be printed using High-NA EUV litho systems. Now, Imec’s findings suggest that MOR's performance can be amplified with environmental conditions during the PEB step.

Imec

Graph showing impact of oxygen injection on the EUV dose required forprinting for both model and commercial MOR. For oxygen concentrations above 21%(oxygen in air atmosphere) a significant reduction in EUV dose is found. (Image credit: Imec)

It should be noted that post-exposure bake is one of the most sensitive steps in the entire lithography flow. PEB activates and drives reactions triggered by photons during the exposure, so small variations of temperature, heating ramp rate, bake time, and atmosphere can have drastic effects on critical dimension (CD), line-edge roughness (LER), and stochastic defect levels, which means that one combination of settings can lead to yield improvement, another can be a yield killer. Changing gas composition inside the PEB module is a big deal not only from the pure semiconductor manufacturing flow point of view, but also from such points of view as long-term material stability, tool oxidation, and safety considerations, just to mention a few.

Imec

A photograph of the BEFORCE tool, short for ‘Bake and EUV system with FTIRand Outgas measurement for Resist evaluation in Controlled Environment’. (Image credit: Imec)

In standard EUV production environments, wafers are exposed in a vacuum and then transferred to a bake module operating under normal cleanroom air containing 21% of oxygen. So, to conduct its experiments, Imec developed a special tool called BEFORCE*, which isolates wafer handling and baking from the surrounding fab environment. The system integrates gas injection and blending capabilities along with built-in photo-speed metrology, which enabled researchers to regulate oxygen contents in the chamber while controlling photoresist performance. To put Imec's discovery into use, foundries will have to ask their fab tool makers to replicate what BEFORCE does during the PEB step.

Imec

A photograph of the BEFORCE tool, short for ‘Bake and EUV system with FTIRand Outgas measurement for Resist evaluation in Controlled Environment’. (Image credit: Imec)

"This is just a first result from the BEFORCE tool: the controlled gas composition provides an additional knob to study the origins of environmental effects on the lithographic variability of MOR materials," said Ivan Pollentier, Senior Researcher at imec. "Equipment manufacturers can use these insights as a guideline to adapt their tools for improved EUV lithography throughput and stability."

*Bake and EUV system with FTIR and Outgas measurement for Resist evaluation in Controlled Environment.

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Anton Shilov is a contributing writer at Tom’s Hardware. Over the past couple of decades, he has covered everything from CPUs and GPUs to supercomputers and from modern process technologies and latest fab tools to high-tech industry trends.