The modern integrated circuit is one of the most complex products that has been engineered to-date. It continues to grow in complexity as the years progress. As a result, very large-scale integrated (VLSI) circuit design now involves massive design teams employing state-of-the art computer-aided design (CAD) tools. One of the oldest, yet most important CAD problems for VLSI circuits is physical design automation, where one needs to compute the best physical layout of millions to billions of circuit components on a tiny silicon surface \cite{Lim08}. The process of mapping an electronic design to a chip involves a number of physical design stages, one of which is clustering. In this paper, we focus on problems in clustering which are critical for more sustainable chips. The clustering problem in combinatorial circuits alone is a source of multiple models. In particular, we consider the problem of clustering combinatorial circuits for delay minimization, when logic replication is not allowed ({\sc CN}). The problem of delay minimization when logic replication is allowed ({\sc CA}) has been well studied, and is known to be solvable in polynomial-time \cite{Wong1}. However, unbounded logic replication can be quite expensive. Thus, {\sc CN} is an important problem. We show that selected variants of {\sc CN} are {\bf NP-hard}. We also obtain approximability and inapproximability results for these problems. A preliminary version of this paper appeared in \cite{Don15}.