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SAW-INT4: System-Aware 4-Bit KV-Cache Quantization for Re...
Jinda Jia, J · 2026-04-22 · via cs.LG updates on arXiv.org

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Abstract:KV-cache memory is a major bottleneck in real-world LLM serving, where systems must simultaneously support latency-sensitive small-batch requests and high-throughput concurrent workloads. Although many KV-cache compression methods improve offline accuracy or compression ratio, they often violate practical serving constraints such as paged memory layouts, regular memory access, and fused attention execution, limiting their effectiveness in deployment.
In this work, we identify the minimal set of 4-bit KV-cache quantization methods that remain viable under these constraints. Our central finding is that a simple design--token-wise INT4 quantization with block-diagonal Hadamard rotation--consistently achieves the best accuracy-efficiency trade-off. Across multiple models and benchmarks, this approach recovers nearly all of the accuracy lost by naive INT4, while more complex methods such as vector quantization and Hessian-aware quantization provide only marginal additional gains once serving compatibility is taken into account.
To make this practical, we implement a fused rotation-quantization kernel that integrates directly into paged KV-cache layouts and introduces zero measurable end-to-end overhead, matching plain INT4 throughput across concurrency levels. Our results show that effective KV-cache compression is fundamentally a systems co-design problem: under real serving constraints, lightweight block-diagonal Hadamard rotation is a viable method that delivers near-lossless accuracy without sacrificing serving efficiency.
Subjects: Machine Learning (cs.LG)
Cite as: arXiv:2604.19157 [cs.LG]
  (or arXiv:2604.19157v1 [cs.LG] for this version)
  https://doi.org/10.48550/arXiv.2604.19157

arXiv-issued DOI via DataCite (pending registration)

Submission history

From: Jinda Jia [view email]
[v1] Tue, 21 Apr 2026 07:12:23 UTC (17,578 KB)