Abstract:The primary goal of Design Verification (DV) is to ensure that a proposed chip design implementation (either in code, or physical form) exactly matches its specification and is free of functional errors in order to avoid costly re-designs. Achieving this often demands extensive manual interpretation, translating the specification document into a formal, testable representation. While AI has made progress in DV, current approaches typically focus on narrow, isolated tasks rather than full end-to-end specification compliance of modern chip designs, failing to capture the complexity of real-world verification. Our method automatically formalizes natural language memory chip specifications, for industry relevant Dynamic Random Access Memory (DRAM) standards, into a formal representation called DRAMPyML that can be used for downstream DV tasks like the generation of SystemVerilog assertions, stimulus, and functional coverage. We also release our benchmarking dataset, DRAMBench, which can be used to evaluate the evolution of model capabilities (and new approaches) at hardware autoformalization.
| Subjects: | Hardware Architecture (cs.AR); Machine Learning (cs.LG) |
| Cite as: | arXiv:2605.00058 [cs.AR] |
| (or arXiv:2605.00058v1 [cs.AR] for this version) | |
| https://doi.org/10.48550/arXiv.2605.00058 arXiv-issued DOI via DataCite (pending registration) |
|
| Journal reference: | ICLR Verif-AI 2 Workshop 2026 |
From: Jan Ole Ernst [view email]
[v1]
Thu, 30 Apr 2026 02:01:48 UTC (457 KB)
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