Abstract:Modern Deep Learning (DL) workloads are increasingly deployed in safety-critical domains, such as automotive systems and hyperscale data centers, where transient hardware faults pose a serious threat to system reliability. These workloads are highly memory-intensive, and their correct functionality strongly depends on model parameters stored in memory, which are typically protected using Error Correction Codes (ECCs). In this work, we study ECC's impact on such models and propose two lightweight alternatives to ECCs that achieve superior reliability. The first approach, MSET, selectively hardens the most vulnerable bits in CNN and ViT parameters, while the second approach, CEP, provides fine-grained protection for all parameter bits. Experimental results demonstrate that both methods significantly enhance the reliability of large CNNs and ViTs, mostly outperforming conventional Single Error Detection Double Error Correction (SECDED) ECC schemes, with no memory overhead and, in fact, with considerably lower area and delay characteristics when compared to SECDEC. Experimental results indicate that ViTs can be effectively protected by merely protecting their highest exponent bits in FP16 and FP32 representations. Furthermore, applying the CEP technique can guarantee the resilience of DNNs by up to one order of magnitude higher BERs, with a 3.5x lower area overhead and 7x faster decoder compared to SECDED ECC.
| Comments: | 7 pages, 7 figures, 3 tables. The paper is accepted at IEEE IOLTS'26 |
| Subjects: | Hardware Architecture (cs.AR); Machine Learning (cs.LG) |
| Cite as: | arXiv:2605.07417 [cs.AR] |
| (or arXiv:2605.07417v1 [cs.AR] for this version) | |
| https://doi.org/10.48550/arXiv.2605.07417 arXiv-issued DOI via DataCite (pending registration) |
From: Mohammad Hasan Ahmadilivani [view email]
[v1]
Fri, 8 May 2026 08:11:15 UTC (370 KB)
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