Abstract:Neural networks with a latency requirement on the order of microseconds, like the ones used at the CERN Large Hadron Collider, are typically deployed on FPGAs fully unrolled and pipelined. A bottleneck for the deployment of such neural networks is area utilization, which is directly related to the required constant matrix-vector multiplication (CMVM) operations. In this work, we propose an efficient algorithm for implementing CMVM operations with distributed arithmetic on FPGAs that simultaneously optimizes for area consumption and latency. The algorithm achieves resource reduction similar to state-of-the-art algorithms while being significantly faster to compute. The proposed algorithm is open-sourced and integrated into the \texttt{hls4ml} library, a free and open-source library for running real-time neural network inference on FPGAs. We show that the proposed algorithm can reduce on-chip resources by up to a third for realistic, highly quantized neural networks while simultaneously reducing latency, enabling the implementation of previously infeasible networks.
| Subjects: | Hardware Architecture (cs.AR); Machine Learning (cs.LG); High Energy Physics - Experiment (hep-ex) |
| ACM classes: | B.2.4; B.6 |
| Cite as: | arXiv:2507.04535 [cs.AR] |
| (or arXiv:2507.04535v2 [cs.AR] for this version) | |
| https://doi.org/10.48550/arXiv.2507.04535 arXiv-issued DOI via DataCite |
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| Journal reference: | ACM Trans. Reconfig. Technol. Syst., Vol. 19, No. 1, Article 13. (March 2026) |
| Related DOI: | https://doi.org/10.1145/3777387
DOI(s) linking to related resources |
From: Chang Sun [view email]
[v1]
Sun, 6 Jul 2025 21:01:32 UTC (558 KB)
[v2]
Fri, 24 Apr 2026 08:59:09 UTC (628 KB)
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