At the 2026 SPIE Advanced Lithography + Patterning conference, IBM Research will present a connected series of talks that form a unified roadmap for the future of logic patterning — from the physics of image formation to full‑flow module performance and device‑level electrical results. Together, they’ll show how the industry can move from research into next-generation devices, and starting to build them at scale.

Throughout the week, researchers from IBM will present several new pieces of work that together show how several technologies, including High‑NA EUV, polarization control, stochastic‑risk reduction, next‑generation masks and resists, will converge to push the boundaries of semiconductor fabrication. In concert, these breakthroughs will result in both dimensional and edge placement error (EPE) scaling, while maintaining a sharp focus on chip manufacturability and cost of ownership.

The roadmap for High NA EUV insertion and EPE scaling

In her keynote at the Advances in Patterning Materials and Processes track of the conference, IBM Research Senior Manager for Patterning and Bonding Solutions, Luciana Meli will outline how High‑NA EUV and other resolution‑enhancement techniques create the necessary headroom to continue scaling both critical dimensions and EPE. Her results indicate clear progress toward High‑NA manufacturing readiness, providing the capability needed to extend patterning and EPE control beyond the 2 nm node. IBM unveiled the world’s first 2 nm node chip back in 2021. 

In her talk, Meli will further detail the technical and cost trade‑offs involved and the corresponding shifts required in the lithography roadmap to meet future scaling targets.

The physics lever: Driving k₁ lower

IBM lithography researcher Martin Burkhardt will also give a presentation at the conference, outlining how the industry can continue shrinking device dimensions and EPE in EUV lithography by pushing the k₁ factor (a representation of the limit of a technology’s resolution) lower and extending the utility of both Low‑NA and High‑NA EUV. He will demonstrate how imaging quality is increasingly dominated by polarization, fading, and bias, and show that there is a strong value proposition for transverse-electric, or TE‑polarized illumination to achieve stable, high‑quality imaging through pitch.

Looking beyond High‑NA EUV

To scale past the limits of High‑NA EUV, the industry must begin to think about what lithography technologies will be required in the next decade. IBM Distinguished Engineer Allen Gabor will present a next‑generation roadmap that spans advanced tooling concepts, predictive resist metrics, and large‑format mask technologies capable of supporting sub‑5‑nm pitch imaging. These advances bridge the gap between lab research and mass-producing the next generation of devices by linking lithography physics, materials innovation, and manufacturable nodes.

Quantifying the performance benefit: Three application‑level proof points

Three further researchers will give talks at the conference that illustrate the work being done now to improve device scaling:

Gate patterning: Single‑exposure EUV gate patterning is approaching fundamental limits as stochastic noise drives line width roughness (LWR) and local critical dimension uniformity (LCDU) challenges at advanced nodes. These have a direct impact on transistor variability and performance. By co‑optimizing source, resist, and mask, including 3‑beam illumination and next‑generation materials, IBM researcher Gopal Kenath will show there could be dramatic reductions in low‑frequency and overall roughness below 50 nm pitch, breaking the Low‑NA scaling relationship and opening new pathways for future gate scaling.

Contact hole patterning: For contact holes, IBM researcher Dario Goldfarb will quantify the real‑world performance differences between 0.55 NA EUV and 0.33 NA EUV. Using both chemically applied resist (CAR) and metal oxide resist (MOR), the work evaluates critical dimension (CD) and pitch scaling, as well as other concerns including mask error enhancement factor (MEEF), depth of focus (DOF), local critical dimension uniformity (LCDU), and stochastic defectivity, establishing when and how High‑NA delivers yield‑relevant improvements for 2D features at an advantageous cost.

Metal patterning and electrical relevance: Turning imaging into integration results, IBM researcher Chris Penny will compare damascene copper and subtractive ruthenium flows patterned with both Low‑NA and High‑NA EUV. Through detailed characterization, the work will provide a clear, head‑to‑head assessment of the patterning and integration choices needed to deliver high‑fidelity interconnects that meet next‑gen performance targets.

Tying all the pieces together

Across the presentations, the IBM Research team will showcase an integrated R&D pipeline that converts foundational imaging breakthroughs into integration‑ready process modules — and ultimately into device‑level performance gains. From advances in polarization‑engineered imaging to High‑NA interconnect demonstrations, each contribution reinforces a unified roadmap for scaling in the AI era.

Collectively, the 16 technical talks highlight the strength of the IBM semiconductor innovation engine, spanning logic lithography, advanced packaging, and metrology. These efforts are further amplified by our partners across the Albany ecosystem — including TEL, Nova, Lam, ASML, Fractilia, and Brookhaven National Laboratory — whose collaboration accelerates progress throughout the semiconductor stack and strengthens the entire innovation pipeline.

Below is the full list of IBM and our partners' presentations at this year's conference: