Since the advent of microprocessors, semiconductor manufacturers have tried to pack more and more transistors into a given area to boost the performance capabilities of machines. Infinite growth is tricky, though: As transistors have gotten smaller and smaller, we’ve begun to approach the limits of how many can fit onto a chip, requiring creative solutions to these spatial limitations.

Enter the nanostack, a new chip architecture from IBM that makes it possible to build transistors in three dimensions. This innovation represents a paradigm shift. With the nanostack, IBM is unlocking the Z axis for scaling, compared to the past 60-plus years of scaling that have happened in just two dimensions: the X and Y axes. Just as in a high-density cityscape, building upward on a given footprint means more effective square footage. Using this same logic, this new technology unlocks a nearly two times greater number of transistors per unit area over the nanosheet technology IBM used in its 2 nm node chips. Here, IBM researchers figured out how to make 3D devices work by stacking silicon wafers and their constituent transistors on top of each other.

The resulting density is impressive — nearly 100 billion transistors on a chip the size of a fingernail. Initial performance projections show 70% less energy consumption compared to 2nm node chip technologies, as well as 50% speedup over chips using that existing transistor node. This means chips built on nanostack technology would be faster for AI model training and inference, laptop and mobile phone batteries would last longer, and devices could consume less power to achieve the same result.

Announced on Thursday, this breakthrough from IBM is the key to overcoming the existing spatial limitations of microchips to increase transistor density.

What is a nanostack?

Fundamentally, a nanostack is a stack of nanosheets. Nanosheets were developed by IBM and introduced in 2017. They surpassed the dominant fin field-effect transistor (FinFET) technology with gate-all-around (GAA) transistors. This change made it possible to pack transistors more closely without the energy leakage that could happen in such a small space.

But describing the nanostack as just stacked nanosheets belies the true complexity of this new device class. One huge advancement, for example, is that n-type and p-type transistors can be stacked sequentially, rather than being situated side by side. Crucially, separating n- and p-type devices means power and signal can be routed through separate devices.

The two flavors of transistor are built from semiconductor materials that are intentionally “doped” to control how electric current flows. In an n-type transistor, extra electrons are introduced (typically by adding elements like phosphorus to silicon), so negatively charged carriers dominate conduction. In contrast, a p-type transistor is doped with elements like boron that create “holes” (positive charge carriers), allowing current to flow through the movement of these vacancies.

The performance of each type can be enhanced by using different materials. By separating them in a device, IBM is unlocking the possibility to experiment with new materials that optimize the traits of each transistor type, said Nelson Felix, director of technical business development for semiconductors at IBM Research.

Building nanostacks requires new fabrication techniques. The relationship between sheets matters, too. The transistors in nanostacks are situated in alternating arrangements like bricks, rather than one right above the other. Coupled with an extremely tight sub-18-nanometer Back end of line is a stage of semiconductor manufacturing that comes after a wafer is patterned with devices. It describes the network of wires that connect the transistors on a chip.back end of line pitch, nanostacks unlock greater density per unit area.

Why does the world need a new transistor technology?

The simple answer: to overcome some of the challenges that come with transistor density.

“We are running out of tricks to be able to put them closer and closer together, given their different sets of materials,” Felix said.

Intel co-founder Gordon Moore predicted in 1965 that the density of transistors on a chip would double every year. A decade later, though, he revised his prediction, now known as Moore’s Law, to about every two years. It was a subtle acknowledgment and foreshadowing that scaling transistor density brings new challenges.

As an industry, we're running into a fundamental limitation about how closely we can put two different types of transistors together. So instead of building them side by side, we’re stacking them. This lets us shrink the circuit and independently address the two types of transistors.

“We always talked about, even 10, 15 years ago, hitting a brick wall, that at some point transistor scaling would stop just because we couldn’t get there,” said IBM Research scientist Griselda Bonilla, who specializes in semiconductors. “But the innovations in materials and tools have really helped spur the development of these technologies. It’s amazing when you think about it.”

By reimagining transistor architecture, nanostack technology is expected to extend logic technology scaling to 2040.

What makes nanostacks difficult?

While nanostacks break free of the scaling constraints of the two-dimensional era, they introduce new challenges.

The new challenges nanostacks introduce are two-fold. The first is wafer alignment and uniformity: By relying on wafer-to-wafer bonding, it requires tightly controlling how flat the wafers are, and proper alignments of transistors relative to one another. A key part of addressing this problem is a thin oxide dielectric layer, called the bonding layer, used between transistor layers to minimize parasitic capacitance and resistance.

The second is that wiring up transistors is more difficult because wires are now smaller, and they have to be mounted across multiple levels of transistors. New, high-tech lithography techniques are helping to address this challenge. More on that later.

What benefits is nanostack technology unlocking?

Now that we’ve decoupled p-type and n-type transistors, we’re free to explore new materials sets for each of them. In the past, material choice was a compromise — what material works best for making p-type transistors isn’t necessarily what’s best for n-type. And at this nanoscale, being able to explore material sets that are optimized for the function of each pair is important.

The nanostack architecture is more flexible, said Tenko Yamashita, senior manager for advanced logic pathfinding technology at IBM Research. “You can put n-type on top of p-type, or p-type on top of n-type, depending on what kind of channel material and process you want,” he said.

Nanostacks get their power delivery on the backside of the wafer, rather than the typical front, where signal is delivered. This switch up, called dual backside power delivery (BPD) or backside power distribution network (BSPDN), helps to improve chip density.

With an increased density of transistors, nanostack chips offer energy savings while also delivering faster computation. The result in performance is 40% greater on-chip memory, Yamashita said.

What innovations are making this possible?

“Nanostack is happening today because of some key technologies that were not available in the past,” said Huiming Bu, vice president of IBM Semiconductors Global R&D. Chief among these developments are the industry progress on wafer-level bonding, and the maturation of BSPDN technology.

Building this new generation of high-density chips also requires special tools for etching transistors into silicon. IBM will be able to do this thanks to the High Numerical Aperture Extreme Ultraviolet (High NA EUV) lithography equipment at the Albany Nanotech Complex, which is slated to be available later this year.

High NA EUV, developed by ASML, is the next generation of printing technology needed to produce future generations of chips. It’s absolutely necessary to make chips with sub-1nm transistors, with any sort of reliability, said Bonilla. Etching the 16-nanometer-pitch wires between transistors can theoretically be done with existing processes, patterning and etching circuit designs onto wafers in small steps over and over. But this workaround takes many steps and is prone to errors — broken lines and squiggly patterns, for example.

“With high NA EUV, you can do that in a single step. And that improves your yield because you’re not processing over and over again to try to get the line," said Bonilla.

"ASML is proud to be engaged early in the development of nanostack architecture, which relies on the higher resolution and tighter process control enabled by High NA EUV technology," said Christophe Fouquet, president and CEO of ASML. "Advanced lithography's improved patterning and reduced process complexity is being leveraged to unlock the potential of exciting new innovations, and IBM's nanostack technology is a prime example,” Fouquet said.

What’s next?

As we enter the nanostack era, IBM is changing the equation for logic scaling. No longer is the question how many transistors can be packed into a given two-dimensional space — we’ve changed the parameters by moving into three dimensions.

“We congratulate our partner IBM on its new nanostack architecture, which reflects real progress in 3D logic scaling," said Rich Wise, vice president for the Aether product line at Lam Research, a major supplier of wafer fabrication equipment. This dry EUV photoresist technology does away with traditional wet chemical methods to improve resolution, productivity, and yield for transferring circuit patterns onto silicon. Along with several other semiconductor process tools, it will support high-yield production for this new -generation of chip technology. "This achievement builds on our collaborative innovations in advanced dry EUV photoresists. Advanced device architectures demand atomic-scale precision — and Lam's Aether dry resist delivers it, enabling chipmakers to unlock the full resolution potential of High NA EUV,” Wise added.

Moving forward, IBM Research scientists will continue to experiment with new materials that improve the performance of n- and p-type transistors. Even as we approach spatial limits (7 angstroms approaches the diameter of just a few atoms), performance improvements can be eked out by optimizing materials.

“Nanostack represents the latest chapter in the long history of IBM and TEL collaboration, helping enable new eras in logic devices,” said Toshiki Kawai, president and CEO at Tokyo Electron (TEL), which has been an IBM partner in semiconductor innovation for more than two decades. “As we look ahead, continued innovation in lithography, etch, and bonding, together with related enabling technologies, through close collaboration between IBM and TEL — will be key to advancing this technology and shaping its evolution over the coming decade.”

On top of all the technical innovations that have come together to make nanostack architecture possible, several key areas are needed in the next few years to get the nanostack ready for industry adoption, Bu said. These include thin dielectric bonding with thermally conductive material, which will help improve heat transfer in increasingly tight spaces; improved chip backside and bevel manufacturing processes; 3D metrology and inspection for quality control; and electronic design automation compatible with these new 3D chip designs. Bu and his team are working on these now to ensure the semiconductor industry is ready to scale with nanostack technology as quickly as possible.