Adaptive bias decoder for non-volatile memory system
Silicon Storage Technology, Inc., San Jose, CA, has been assigned a patent (12518829) developed by Tran; Hieu Van, Vu; Thuan, Hong; Stanley, Trinh; Stephen, Ly; Anh, San Jose, CA, Do; Nhan, Saratoga, CA, and Reiten; Mark, Alamo, CA, for an “adaptive bias decoder for non-volatile memory system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “In one example, a non-volatile memory system, comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to the source line of the array during operation.”

The patent application was filed on 2023-12-11 (18/536186).

Coarse and fine programming of non-volatile memory cells
Silicon Storage Technology, Inc., San Jose, CA, has been assigned a patent (12511073) developed by Song; Yi, San Jose, CA, Kim; Jinho, Saratoga, CA, and Liu; Xian, Sunnyvale, CA, for “coarse and fine programming of non-volatile memory cells.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method of programming non-volatile memory cells comprising determining a target read current for respective ones of the memory cells based upon incoming data, associating respective ones of the memory cells with a respective one of a plurality of cell groups based upon the determined target read current for the respective memory cell being within a target read current range associated with the respective cell group, fast programming respective ones of the memory cells to a coarse target read current associated with the cell group to which the respective memory cell is associated, wherein the coarse target read current for respective ones of the cell groups is greater than the target read current range for the respective cell group, and then slow programming respective ones of the memory cells until the target read current determined for the respective memory cell is achieved.”

The patent application was filed on 2024-04-26 (18/648219).

Method of forming a device with planar split gate non-volatile memory cells, planar HV devices, and FinFET logic devices on a substrate
Silicon Storage Technology, Inc., San Jose, CA, has been assigned a patent (12453136) developed by Jourba; Serguei, Aix en Provence, France, Decobert; Catherine, Pourrieres, France, Zhou; Feng, Fremont, CA, Kim; Jinho, Saratoga, CA, Liu; Xian, Sunnyvale, CA, and Do; Nhan, Saratoga, CA, for a “method of forming a device with planar split gate non-volatile memory cells, planar HV devices, and FinFET logic devices on a substrate.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method of forming a device on a silicon substrate having first, second and third areas includes recessing an upper substrate surface in the first and third areas, forming an upwardly extending silicon fin in the second area, forming first source, drain and channel regions in the first area, forming second source, drain and channel regions in the fin, forming third source, drain and channel regions in the third area, forming a floating gate over a first portion of the first channel region using a first polysilicon deposition, forming an erase gate over the first source region and a device gate over the third channel region using a second polysilicon deposition, and forming a word line gate over a second portion of the first channel region, a control gate over the floating gate, and a logic gate over the second channel region using a metal deposition.”

The patent application was filed on 2022-05-25 (17/824812).

Output block for array of non-volatile memory cells
Silicon Storage Technology, Inc., San Jose, CA, has been assigned a patent (12444449) developed by Tran; Hieu Van, San Jose, CA, Vu; Hoa, Milpitas, CA, Trinh; Stephen, Hong; Stanley, Vu; Thuan, San Jose, CA, Le; Nghia, Nguyen; Duc, and Pham; Hien, Ho Chi Minh, Vietnam, for an “output block for array of non-volatile memory cells.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns, the array comprising a first bit line coupled to a first column of non-volatile memory cells and a second bit line coupled to a second column of non-volatile memory cells; and an output block coupled to the array, the output block comprising: a current-to-voltage converter to convert a first current on the first bit line into a first voltage and to convert a second current on the second bit line into a second voltage; and an analog-to-digital converter to convert one or more of the first voltage and the second voltage into a set of output bits.”

The patent application was filed on 2023-05-09 (18/195322).