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This technique is similar to what HBM4 memory currently does, with the base die being a logic die to better integrate compute solutions underneath for packet tracing and data preparation for entering and exiting HBM. However, Qualcomm aims to achieve higher efficiency and more optimized data movement, with a 6x increase in bandwidth per watt compared to the current HBM specification, likely HBM4. HBC Gen 1 achieved 133 TB/s of bandwidth on the AI250 accelerator, a 18x increase over the LPDDR5X currently used in the AI200 card from Qualcomm. The company also claims there is a viable roadmap for using HBC across many Qualcomm AI accelerators, with HBC Gen 1 shipping with the AI250 AI accelerator in mid-2027. The next-generation HBC Gen 2 is expected to yield further significant gains in bandwidth.
Currently, it is unclear where Qualcomm plans to source the LPDDR memory, which LPDDR memory version is used in HBC, and where the company plans to package this. Qualcomm is known for manufacturing its Snapdragon SoCs at TSMC, but the compute die could be manufactured by any memory maker partnering for the HBC launch. The most logical choice is Samsung Foundry, which manufactures both LPDDR in-house and offers custom logic manufacturing. However, this has yet to be confirmed by Qualcomm.
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