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We present VeriCache, the first inference framework that ensures the same output as full-KV-cache decoding but largely preserves the high decoding throughput of a range of KV cache compression algorithms. VeriCache uses the compressed KV cache to draft tokens, then verifies them against the full KV cache. While it may seem like just speculative decoding, VeriCache requires addressing a key system challenge to work-keeping the full KV cache out of GPU memory and minimizing the overhead of swapping it in for verification. The insight is two-fold: (1) compressed-KV decoding can be parallelized with full-KV swap, because one is HBM-bandwidth-bound and the other is PCIe/network-bound, and (2) the compressed KV cache often produces output similar to the full KV cache, allowing a long drafting horizon to amortize each full-KV swap.
VeriCache applies to both long-context decoding and remote prefix caching, supports a broad family of token-dropping and quantization methods through a uniform compressor interface, and composes with traditional speculative decoding. Experimental results show that VeriCache achieves up to 4X higher throughput than full-KV inference while producing identical outputs.
| Subjects: | Hardware Architecture (cs.AR); Machine Learning (cs.LG) |
| Cite as: | arXiv:2605.17613 [cs.AR] |
| (or arXiv:2605.17613v1 [cs.AR] for this version) | |
| https://doi.org/10.48550/arXiv.2605.17613 arXiv-issued DOI via DataCite (pending registration) |
From: Jiayi Yao [view email]
[v1]
Sun, 17 May 2026 19:18:39 UTC (435 KB)
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