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By Brian Tristam Williams
Diodes Incorporated has introduced the PI6CG33A06, a six-output, ultra-low-jitter clock generator for PCI Express 7.0 systems, while maintaining support for earlier PCIe generations.
The PCIe 7.0 clock generator is aimed at servers, networking equipment, high-performance computing systems and data centre platforms used in AI infrastructure. It was announced at the PCI-SIG Developers Conference in Santa Clara.
The PI6CG33A06 generates 25 MHz and 100 MHz reference clocks and achieves RMS jitter below 30 fs. That is below the 67 fs maximum requirement for the PCIe 7.0 specification and below the 80 fs level defined by Intel’s CK440Q specification.
At these data rates, the timing budget is tight. Diodes says the part provides a stable reference clock for 128.0 GT/s PCIe links, targeting 800G and 1.6T networking systems as well as advanced AI accelerators. As previously reported by eeNews Europe when PCIe 8.0 was outlined for AI infrastructure, the PCIe roadmap continues to push both bandwidth and signal-integrity requirements upwards.
The PI6CG33A06 uses Diodes’ low-power, high-speed current-steering logic technology with integrated termination. The company says this cuts clock-related power consumption by at least 50% compared with traditional HCSL implementations.
The integrated termination also removes the need for up to 24 external resistors. That reduces the bill of materials and simplifies PCB layout, while freeing board area in dense server designs where power delivery, memory placement and cooling already compete for space.
Each of the six outputs has an individual output-enable pin, allowing designers to shut down or manage outputs independently. The device supports Intel CK440Q-Lite specifications, so it can be used in existing server clock architectures while improving timing margin.
The PCIe 7.0 clock generator is supplied in a 40-pin, 5 mm x 5 mm VQFN package. Diodes lists pricing from $2.80 in 3,000-piece quantities.
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