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Photonics is rapidly becoming a key technology for AI in the datacentre. Using light to connect chiplets and memory can significantly reduce the power consumption of AI systems, a factor that is limiting the overall performance.

Companies are buying up key photonic technology suppliers, while research labs are pushing back the boundaries of what is possible.

“The rapid growth of AI workloads is creating immense pressure on the entire data centre stack, with the interconnect fabric emerging as a major bottleneck,” said Sameh Boujelbene, Vice President, Market Research at Dell’Oro Group. “The industry has long recognized the critical role of Co-Packaged Optics in addressing power, performance, and density challenges.”

“The data centre pluggable optics market continues to expand strongly, reaching $15.5 billion in 2025. We expect the market to grow at a compound annual growth rate (CAGR) of 17% from 2025 through 2030, surpassing $34 billion by the end of the forecast period. In addition, co-packaged optics (CPO) will emerge as a rapidly growing segment, contributing more than $9 billion in revenue by 2030. Over the same period, the share of transceivers incorporating silicon photonics modulators is projected to increase from 43% in 2025 to 76% by 2030,” said Vladimir Kozlov, CEO and Chief Analyst at LightCounting.

One example of the importance of the sector is the recent deal by Marvell to buy Polariton Technologies. This follows Marvell’s $3.5bn acquisition of Celestial AI back in February 2026 for the optical interconnect between chiplets.

• Europe drives to dominate photonics 

The Polariton deal adds advanced modulation capabilities based on plasmonic technology that enable continued scaling in bandwidth, power efficiency, and integration for next-generation coherent and optical interconnect platforms.

While the transition to 1.6Tbit/s connections is underway to connect up AI servers, the industry is already advancing toward 3.2T and beyond. Polariton’s plasmonics-based modulation technology is aimed at next-generation optical interconnects in a highly compact form factor. Marvell sees the combination of plasmonics with silicon photonics as a way to extend the performance of optical interconnects and supports the continued scaling of next-generation coherent and optical interconnects.

Co-packaged optics

Co-packaging optics (CPO) with the chips is a key technology. The increase in AI workloads has exposed a critical bottleneck in electrical interconnects. CPO provides massive increases in bandwidth that contribute to large gains in compute, power and space efficiency. However, the complexity of CPO systems presents challenges around integration, interoperability, reliability and scaling across a diverse supply chain.

STMicroelectronics returned to the photonics business last year with a revamped process technology that it offers as a foundry service. Its PIC100 technology is now in high-volume production on 300 mm wafers for leading hyperscalers, with plans to quadruple capacity by 2027 and further expand in 2028.

The 800G and 1.6T PIC100 transceivers enable higher bandwidth, lower latency, and greater energy efficiency as AI workloads surge.

“Following the announcement of its new silicon photonics technology in February 2025, ST is now entering high-volume production for leading hyperscalers. The combination of our technology platform and the superior scale of our 300 mm manufacturing lines gives us a unique competitive advantage to support the AI infrastructure super-cycle,” said Fabio Gualandris, President, Quality, Manufacturing & Technology at ST. “Looking ahead, we are planning and executing on capacity expansions to enable more than quadrupling of production by 2027. This fast expansion is fully underpinned by customers’ long-term capacity reservation commitments.”

ST is also developing a process with through silicon vias (TSV) to assist with the integration of photonics and silicon. The PIC100 TSV platform boosts optical connectivity density, module integration, and system-level thermal efficiency for chip-to-chip interconnect and co-packaged optics.

At the same time Lightmatter in the US is working within the Open Compute Project (OCP) to create open specifications for a shared reference architecture enabling interoperable CPO in next-generation AI systems.

The collaboration includes manufacturers Celestica, Flex, Foxconn Interconnect Technology and Quanta Cloud Technology as well as Corning, Dell Technologies, Qualcomm and Keysight.

This directly addresses the need for collaborative open standards that will enable a robust ecosystem, high-volume production and seamless integration of CPO in hyperscale data centres.

“The AI revolution is at a pivotal moment, and we must ensure interoperable solutions that can be produced and deployed at scale across the industry’s diverse ecosystem,” said Nick Harris, founder and CEO at Lightmatter. “We believe the answer is in open collaboration. By working with the OCP community, we can define the standards that will unlock the full potential of CPO, enabling a vibrant ecosystem across the hyperscaler supply chain. We are already seeing strong support from industry leaders who recognize the urgency of this effort.”

This collaboration proposes to bring together AI system architects, advanced manufacturing partners, and networking leaders to align on a shared vision and roadmap for CPO. The goal is to develop open standards for components and systems and to establish a framework for interoperability testing and certification.

“As Qualcomm Technologies continues to scale its high-performance, power-efficient compute architecture from the edge into the hyperscale data centre, the need for a collaborative and open interconnect framework has never been greater,” said Tony Chan Carusone, Technology Executive at Qualcomm Technologies and former CTO of Alphawave Semi. “A shared reference architecture for Co-Packaged Optics is essential for fostering a diverse ecosystem that can deliver the interoperability and scalability required for the next generation of AI infrastructure.” 

Connector giant Molex is making sure it is not left out in this area, planning to buy Teramount in Israel for its CPO technology. Teramount’s TeraVERSE platform is based on a universal photonic coupler and wafer-level self-aligning optics that provides a pragmatic, field-serviceable interface between optical fibre and silicon photonics chips. This is a passively-aligned, detachable system that supports large assembly tolerances and semiconductor-grade wafer-level processes. Compared with active alignment methods, passive alignment is materially more scalable as CPO moves toward volume production and so can enable faster data rates necessary to support AI adoption while consuming less energy to reduce power and cooling demands in hyperscale data centres.

“TeraVERSE technology fills a crucial gap in the CPO stack, offering an advantaged and strategic complement to our optical solutions portfolio. A practical, detachable fibre-to-chip interface is a foundational element for mainstream CPO adoption,” said Aldo Lopez, president of Datacom Solutions at Molex. “Combining Teramount’s IP and engineering talent with Molex’s portfolio, manufacturing scale, supply-chain expertise and systems know-how gives customers an integrated, high-volume path to deploy scalable CPO.”

“Harnessing Molex’s global scale and system-level expertise with Teramount’s innovation expertise and detachable, wafer-level coupling technology creates a real pathway for scalable, high-density CPO,” said Hesham Taha, CEO and co-founder of Teramount. “Joining forces with Molex will enable us to accelerate delivery of a manufacturable, serviceable fibre-to-chip interface that meets the pressing needs of AI and hyperscale data centres.”

Micro-transfer printing

Imec in Belgium is pushing back the boundaries of photonics with the heterogeneous integration of new materials onto silicon photonics platforms. This will enable next-generation electro-optical modulators and detectors for both short-reach and short-haul interconnects.

One key material is lithium niobate (LiNbO₃), renowned for its high electro-optic coefficient, making it an excellent fit for high-speed optical communication systems. Another contender is lithium tantalate (LiTaO₃), valued for its electro-optic stability, high damage threshold, and UV transparency – qualities that make it ideal for high-power, temperature-sensitive applications, and systems operating at shorter wavelengths.

However, both materials contain lithium, which complicates their compatibility with standard CMOS fabrication processes. And integrating other components, such as high-speed photodetectors, alongside these materials is also far from trivial.

Several integration approaches have been evaluated for integrating devices built with these technologies into silicon devices. Wafer bonding, for instance, has been demonstrated with lithium niobate, but it remains costly and inefficient as most of the material must be removed after bonding and many additional post-bonding processing steps are needed.

Instead, imec has developed a micro-transfer printing process that can integrate LiNbO₃ and LiTaO₃ onto a silicon photonics platform. It showed the first heterogeneous integration of a LiTaO₃ modulator on a silicon photonic integrated circuit using a micro-transfer printing technique previously applied to lithium niobate, the approach ensures full compatibility with the entire wafer stack. It enables seamless co-integration with other components such as heaters, filters, and germanium photodetectors – without compromising their performance.

“Building on our work with lithium niobate, we found that the same micro-transfer printing technique can be applied to lithium tantalate as well, demonstrating its exceptional versatility,” said imec researcher Margot Niels. “This gives us strong confidence that, as new materials emerge, we will be able to integrate them just as effectively on silicon photonics – thus laying the groundwork for the next generations of optical interconnects.”

At this year’s European Conference on Optical Communication (ECOC), researchers from imec and Ghent University showed a 320Gbit/s unamplified optical link over 2 km of standard single-mode fibre using high-speed integrated circuits that are fully compatible with standard CMOS manufacturing.

This proof of concept leverages a high-bandwidth 100GHz germanium photodiode and transfer-printed thin-film lithium niobate Mach-Zehnder modulators (MZMs) onto imec’s silicon photonics platform, co-packaged with custom-designed traveling-wave drivers and transimpedance amplifiers (TIAs).

This is the first such integration of thin-film LiNbO₃ devices on silicon photonics and suggests a path toward optical interconnects delivering 400Gb/s per lane.

Holographic interconnect

At the same time a startup in the UK is developing a holographic technique to implement photonic interconnect. The Wire to Waves platform being developed by AGI Infinity is designed to address the growing bottlenecks in AI computing.

A patent being developed by the company centres on two core elements: Holographic Optical Conductors (HOC), designed to provide optical alternatives to selected electrical interconnects, and Holographic Optical Transistors (HOT). These are transistor‑like optical structures intended to enable switching and logic behaviour within holographically structured materials.

AGI Infinity has completed two simulations validating the core patent claims, demonstrating that both the micro‑scale and nano‑scale elements of the architecture can operate within a single 3D structure.

The unified architecture is intended to explore whether structured light, guided through volumetric holographic media, can support higher‑bandwidth with lower‑latency data movement. This leads to reduced resistive losses, improved thermal characteristics and simplified routing for new optical switching concepts in future AI hardware.

AGI Infinity says it believes the industry is entering a structural transition comparable to the move from planar transistors to 3D stacking. The company’s patent incorporates claim families around Z‑axis stacking, multiplexed addressing, chiplet/interposer embodiments, calibration, redundancy and self‑healing.

Meaningful adoption won’t happen overnight, says the company, but the industry is already moving toward chiplets, advanced packaging and co‑packaged optics. The transition from wires to waves will define the next era of AI. The company says it is in discussions with strategic investors and partners interested in the optical‑enabled AI technology.

Large substrates

Researchers in Germany have also developed a technique to create photonic structures on large substates with atomic-accuracy.

With conventional methods, high-precision nanostructures on photonic components can currently only be produced up to a size of 30 cm. The researchers from the Fraunhofer Institute for Applied Optics and Precision Engineering IOF in Jena, as well as the Institute of Applied Physics (IAP) at Friedrich Schiller University Jena and the Technical University of Ilmenau in Thuringia are developing a machine that creates nanostructures spanning up to one square meter with a positioning accuracy smaller than an atom. The €4m research project, funded by the Deutsche Forschungsgemeinschaft (DFG, German Research Foundation) launches next month.

The 3D nanolithography and nanomeasuring machine will enable the processing and measurement of photonic components with dimensions of up to 1 × 1 × 0.2 meters, three times larger than what is possible with current methods.

“The fact that there are machines for structuring large-area components is, at first glance, nothing unusual,” said Prof. Uwe Zeitner, project leader at Fraunhofer IOF.

“Many modern TV sets have displays that incorporate nanotechnology. But they are nowhere near as precise as we need them to be in various scientific applications. Scientific applications require high-precision nanostructuring. With conventional technologies, such structures can currently only be produced with the necessary precision on photonic components and parts with a size of up to approximately 30 cm.”

“We want to create nanostructures with a positioning accuracy across this surface of up to twenty picometres,” he added. “These are largely unique in their complexity and reflect the long-standing and comprehensive expertise of all partners involved.”

The first project phase over the next three years will see an overall concept developed with key subsystems and proof of the specified parameters. The fully operational machine is expected to be available at Fraunhofer IOF in approximately six years.

www.marvell.com; www.imec-int.com; www.st.com; www.lightmatter.com; www.agiinfinity.ai

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