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By Jean-Pierre Joosting
For many engineers, there are few hardware options to support high-performance AI. Typically, one has to choose between repurposed GPUs that require a full system redesign or running inference directly on embedded CPUs and NPUs at the cost of severe thermal limits and high latency. Earlier USB and M.2 accelerators offered a more modular path at the cost of limited compute and memory capacity. This left developers with an expensive balancing act where they must consider performance, power consumption and flexibility, often sacrificing one or more in the process.
The Gateworks GW16168 M.2 card revives the modularity of earlier M.2 accelerators while significantly advancing the underlying technology. Future upgrades and revisions no longer require replacing otherwise capable industrial SBCs. For example, dedicated AI acceleration can be added directly to platforms such as the i.MX 8M Plus or i.MX 95 applications processors via the M.2 interface. However, these same SBC systems could reach 100% utilisation when running inference workloads. The GW16168 with 16GB of LPDDR4 memory allows these tasks to be offloaded to the card, freeing the host CPU to focus on system logic and I/O. As an added benefit, the common out-of-memory errors encountered when running Vision transformers or LLMs on standard edge modules are no longer an issue.
“The GW16168 illustrates exactly why decoupled AI architectures are the future of edge computing. By combining NXP’s Ara240 DNPU with our industrial-grade design, customers can scale AI performance without redesigning their entire hardware platform,” says Ravi Annavajjhala, Vice President and General Manager, Neural Processing Units, NXP Semiconductors. “This brings flexibility, longevity and cost efficiency to real-world AI deployments.”
One of the biggest challenges in AI deployment is thermal management. High-performance AI systems can draw significant power, with demand often spiking during complex tensor operations. As a result, thermals frequently become the limiting factor. This is especially problematic in space-constrained industrial designs where advanced cooling systems can quickly become costly and impractical. The Gateworks M.2 card has been designed specifically to address this issue by using a passively cooled NXP Ara240 Discrete Neural Processing Unit (DNPU) together with carefully engineered power circuitry, to enable a typical power consumption of 12 W. This lower power envelope reduces heat build-up, enabling reliable operation in sealed, fanless environments while maintaining thermal characteristics aligned with industrial-grade AI hardware. The M.2 card also boasts a decade-long lifespan, thanks to advanced thermal management that reduces wear on the modules.
The GW16168 did not emerge from a standing start. Gateworks has designed and manufactured embedded computer boards in California for over 30 years, and every board in its current portfolio carries an NXP processor. That longstanding dependency has evolved into a formal gold partnership. Today, Gateworks designs single-board computers exclusively with NXP silicon across its product lines, and NXP shares early roadmap access, design documentation and direct engineering collaboration. When NXP acquired AI inference specialist Kinara in 2024 and absorbed the Ara240 Discrete Neural Processing Unit (DNPU) into its portfolio, Gateworks was positioned to move quickly. The kickoff meeting took place at CES in January 2026. The product ships in June.
“We’ve been working with NXP making computer boards for three generations of products,” says Kelly Peralta, VP of Sales and Business Development at Gateworks. “Every board we make has an NXP processor. We work very closely, mutually sharing early design roadmaps, design guidelines and a lot of collaboration to help our customers deploy faster. When we found out that NXP was going to have their own AI accelerator — when they acquired Kinara — we took that seriously.”
NXP’s acquisition of Kinara brought a mature compiler toolchain into the partnership. The Ara Software Development Kit (SDK) functions as an abstraction layer between high-level AI frameworks such as TensorFlow, PyTorch, and ONNX and the DNPU hardware. It handles model conversion, quantisation, and graph optimisation without requiring hardware-specific rewrites. As a result, the GW16168 arrives with software infrastructure already in place. Gateworks’ role is to integrate the card with its own embedded Linux boards and validate the full stack, rather than developing AI runtime software from scratch. NXP maintains the SDK and supports ongoing model migration as AI frameworks evolve.
NVIDIA dominates AI compute at the data centre level. Its GPU architecture, mature CUDA ecosystem, and software tooling make it the default choice when raw throughput is the primary constraint. At the edge, however, the calculus is different. In many cases, industrial applications do not need a GPU. They need sustained, reliable inference under the thermal and power budgets of a sealed enclosure. Further, they need to be able to deploy it at scale without the per-unit cost of a Jetson module.
“NVIDIA is a powerhouse — they are a clear leader in AI infrastructure,” Peralta says. “They are designing high-performance AI, especially for data centres. We have some industrial customers using NVIDIA. But they’re having trouble with the heat generated and power consumption. Gateworks takes a system-level approach — combining processor board, edge AI accelerator and development kits to enable lower-power operation, streamlined integration, and faster time to market for industrial edge applications.”
The GW16168 also reaches customers who were previously locked out of edge AI entirely, including system designers with existing Gateworks single-board computers (SBCs) running NXP i.MX 8M Plus or i.MX 95 processors that need to add AI capability without a full platform redesign. For these users, the M.2 form factor provides a compelling value proposition. The card slots in, the Ara SDK handles model deployment, and the host CPU is freed to continue managing I/O and system logic. Critically, model compatibility carries across as engineers already running TensorFlow or PyTorch workloads on NVIDIA hardware can migrate those same models to the Ara240 without framework changes.
The GW16168 targets applications where edge inference is the operational requirement. Machine vision for production-line defect detection, smart-grid substation monitoring, unmanned-vehicle navigation, predictive maintenance of rotating machinery, and security systems that combine camera feeds with acoustic sensors all fall within this category. Each relies on sustained inference throughput, operates in environments where active cooling is impractical, and demands hardware longevity measured in years rather than product cycles.
Predictive maintenance is particularly well-suited to GW16168. A typical deployment monitors machines using a combination of vibration sensors, thermal cameras, and audio analysis, feeding continuous data streams into models that identify anomalous patterns before failure. These workloads are compute-bounded but not compute-intensive, unlike large language model (LLM) inference. Instead, they require a reliable sub-100ms response and consistent availability over months of unattended operation. Remote substations present a similar constraint profile — the equipment sits in a rural location, physical maintenance visits are expensive, and the consequences of missed anomaly detection are not a delayed product but a grid failure.
“A lot of substations and facilities are in rural areas that are difficult to access; sending people back and forth every day to monitor equipment is not ideal,” says Hailey Terrones, Territory Sales Manager at Gateworks. “The reality is everyone is trying to figure out how to implement AI — even if it’s just to evaluate what is possible. Everyone’s trying to be faster and do more. If they have a plug-and-play way to implement AI on an existing system, they can see how it behaves in a real setting instead of just talking about it.”
The 40 equivalent TOPS (eTOPS) figure sits well above what most edge computer vision workloads consume today. Airport security screening systems, for example, typically operate at under ten TOPS — weapons recognition in a camera stream does not require the same compute density as training a model. The GW16168’s 16 GB of LPDDR4 memory and support for 30-billion-parameter models at INT4 precision extend its useful range into Vision Language Models (VLMs) and smaller LLMs, but the more immediate case is that the card arrives with substantial headroom for inference workloads that today run two or three TOPS. That gap is where the longevity argument lives.
Industrial customers do not retire hardware on consumer upgrade cycles. A Gateworks board deployed inside a rail monitoring system or on a factory floor may run for over a decade without replacement. Further, the software stack it runs must remain maintainable for the same duration. This is where open-source foundations matter. Gateworks has built on open-source Linux for 30 years, ships a Board Support Package (BSP) based on Ubuntu, and validates every peripheral interface before customer release. NXP is currently migrating the Ara SDK from its legacy Kinara-era toolchain to a Yocto-compatible environment, aligning the AI runtime with how embedded Linux systems are typically maintained and updated in the field.
The division of responsibility is deliberate. Gateworks handles the board and integration layers, while NXP owns the Ara SDK and compiler. Customers building OEM products take the validated stack and extend it for their application. This separation means that AI framework updates — such as new ONNX revisions, quantisation improvements, and updated model architectures — flow through NXP’s SDK without requiring hardware changes. The GW16168 also includes hardware-level security features. Secure boot and root of trust are part of the Ara240 architecture, which meets the security requirements of smart grid and industrial monitoring deployments that require tamper resistance.
“Many of today’s AI applications we see today aren’t utilising 40 eTOPS,” says Terrones. “A large number of real-world workloads like image classification and object detection can run on far less, in a single-digit to low double-digit TOPS range, depending on the model and requirements. Even in applications like security screening, where AI is used for real-time image analysis, system design prioritises efficiency and accuracy rather than intensive compute. With 40 eTOPS, you have significant headroom as requirements evolve.
The underlying argument for decoupled AI architecture is that AI compute requirements change faster than the embedded platforms they run on. A single-board computer designed for a rail monitoring application has a useful life measured in years or decades. The AI models it runs, and the hardware needed to execute them efficiently, will change within that window. Tying AI capability to the host processor means that every model upgrade is potentially a platform replacement. Separating them via M.2 means the host platform stays the same, and the accelerator card is the only component that needs to change when compute requirements shift.
The GW16168 is designed and manufactured in the USA, operates across an industrial-grade temperature range, and carries a stated decade-long module lifespan. These specifications reflect the typical procurement requirements of the industrial, defence, and energy sectors. The 12W typical power draw and passive cooling also carry implications beyond thermal management: they reduce the operational energy cost of running inference at scale, which matters in deployments where hundreds or thousands of edge nodes run continuously.
Future iterations of the GW16168 concept will likely track NXP’s DNPU roadmap. Gateworks has stated explicitly that it migrates when NXP migrates — meaning the upgrade path for customers is a card swap rather than a system redesign. Whether that manifests as higher eTOPS at the same power envelope, equivalent performance at reduced power, or expanded memory capacity for larger models will depend on where edge AI workloads are heading. The current design demonstrates that the modularity argument is technically credible at 40 eTOPS and 12 W. The question for the next generation is whether the power and cost curves continue to move in the right direction. Given the trajectory of Ara240’s architecture, there is no reason to expect otherwise.
www.gateworks.com
www.nxp.com
www.nvidia.com
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