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As AI workloads continue to push memory systems to their limits, researchers are looking beyond conventional DRAM and SRAM technologies for new ways to increase capacity, bandwidth and energy efficiency. Belgian research institute imec has now unveiled two advances in ferroelectric memory research that could help address those challenges.

The work, presented at the 2026 IEEE / JSAP Symposium on VLSI Technology & Circuits, focuses on low-voltage ferroelectric capacitors and vertically stacked ferroelectric field-effect transistors (FeFETs), two technologies that could support future high-density memory architectures.

For eeNews Europe readers, the developments are significant because they target one of the semiconductor industry’s biggest bottlenecks: memory scaling in the AI era. The research also highlights potential alternatives to increasingly costly and difficult-to-scale DRAM technologies.

Low-voltage ferroelectric capacitors

Imec reported that its ferroelectric capacitors can operate at around 1.3V while maintaining a high remnant polarization of more than 40 μC/cm² and endurance of at least 10¹³ cycles. These characteristics are considered critical for future DRAM-like memory applications.

Ferroelectric memory has attracted growing interest because it offers non-volatile behaviour and low-voltage operation while also supporting denser integration schemes. As traditional memory technologies approach physical and economic scaling limits, such characteristics are becoming increasingly valuable for AI and data-centric computing systems.

Researchers achieved the latest results by scaling the ferroelectric layer while preserving the electrical characteristics needed for reliable operation.

Vertical FeFET stacking boosts density

In a separate demonstration, imec showcased what it describes as the first functional five-word-line vertical stack of IGZO-based FeFET memory cells. By stacking memory cells vertically, the approach increases storage density without requiring additional chip area.

The researchers also introduced a dual-gate architecture featuring a back-gate to improve erase efficiency, one of the longstanding challenges associated with FeFET technology.

The work points toward future 3D memory architectures that could deliver significantly higher density than conventional planar approaches. According to imec, lessons learned from ferroelectric capacitor development are directly applicable to FeFET optimisation, while the stacking techniques developed for FeFETs could eventually support dense 3D ferroelectric capacitor arrays.

“These advances come at a critical moment for the semiconductor industry,” said Attilio Belmonte, program director at imec. “This work shows how imec’s multidisciplinary expertise, from materials science to advanced 3D integration, enables us to tackle some of the most pressing challenges in memory technology.”

Maarten Rosmeulen, program director at imec, added: “We are exploring multiple paths toward the memory solutions that will be required to sustain the rapid growth of AI and data-intensive applications.”

Toward practical implementation

While both technologies remain at the research stage, imec plans to continue improving endurance and erase performance in FeFETs, as well as further voltage scaling and reliability in ferroelectric capacitors. Future work will also include system-level evaluations and the development of fully integrated 3D memory architectures.

If successful, the technologies could provide complementary routes toward next-generation memory systems capable of meeting the rapidly growing data requirements of AI applications.

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