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TSMC is pushing its 3D chip-stacking roadmap towards finer interconnect pitches and tighter integration as advanced packaging becomes a larger part of performance scaling for AI and high-performance computing designs.

The updated TSMC SoIC roadmap, reported after the company’s 2026 North America Technology Symposium in Santa Clara, points from 6 µm pitches today towards 4.5 µm by 2029. That direction matters because pitch scaling in hybrid-bonded die stacks directly affects the number of vertical interconnects that can be placed between chiplets.

TSMC separately said at its 2026 North America Technology Symposium that A14-to-A14 SoIC is set to be available for production in 2029, providing 1.8x higher die-to-die I/O density than N2-on-N2 SoIC. The company positions the technology as part of its wider 3DFabric advanced packaging family, alongside CoWoS and InFO.

TSMC SoIC roadmap moves beyond lateral scaling

SoIC, or System on Integrated Chips, is TSMC’s 3D stacking technology for heterogeneous chiplet integration. On its 3DFabric technology page, TSMC describes SoIC as an ultra-high-density vertical stacking technology intended to reduce size, increase performance and lower resistance, inductance and capacitance.

The move from face-to-back to face-to-face stacking is the key technical shift. In face-to-back designs, signals still need to pass through more complex routes, including through-silicon vias in the lower die. In face-to-face stacking, the active metal layers of two dies are aligned directly and connected using hybrid copper bonding, shortening the path between chiplets.

According to Tom’s Hardware, Broadcom has cited a real-world signal density of about 1,500 signals/mm² for face-to-back stacking, compared with 14,000 signals/mm² for face-to-face stacking. The practical benefit is higher bandwidth and lower latency between stacked dies, although the thermal and manufacturing challenges do not disappear.

Fujitsu Monaka gives the TSMC SoIC roadmap an early test

Fujitsu’s Monaka processor is one of the first high-profile systems expected to benefit from face-to-face chiplet stacking. Broadcom said in February that it had begun shipping a 2 nm custom compute SoC built on its 3.5D XDSiP platform, which combines 2.5D integration and 3D-IC stacking using face-to-face technology.

The platform is being used for Fujitsu’s Monaka initiative, with Broadcom saying it allows compute, memory and network I/O to scale independently in a compact package. The update follows earlier coverage by eeNews Europe when Broadcom’s 3.5D platform was linked to Fujitsu Monaka.

Monaka is aimed at AI and HPC workloads, and earlier eeNews Europe reporting noted that Fujitsu is using Armv9-A architecture with SVE2 extensions for machine learning and AI workloads. The processor is expected to arrive in 2027, putting it close to the first wave of commercial systems that will show whether high-density face-to-face chiplet stacking can move from roadmap slide to production economics.

Packaging becomes the scaling engine

The TSMC SoIC roadmap sits alongside a broader industry shift. As front-end process gains become more expensive and harder to extract, foundries and chip designers are pushing more performance work into packaging: larger interposers, denser die-to-die links, stacked cache, HBM integration and co-packaged optics.

TSMC’s 2029 target does not mean every advanced processor will use the densest SoIC option. Cost, yield, thermal limits and design complexity will still determine adoption. But the roadmap shows that TSMC is treating vertical integration as a core part of its advanced-node strategy, not as a niche packaging option.

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