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By Asma Adhimi
Siemens and TSMC are deepening their collaboration to push AI-powered automation across semiconductor design workflows. The move builds on an existing partnership and focuses on accelerating advanced node development and improving design efficiency using AI.
For eeNews Europe readers, the announcement highlights how leading EDA vendors and foundries are embedding AI into core chip design flows — an area that directly impacts time-to-market, yield, and competitiveness at advanced nodes.
At the center of the collaboration is Siemens’ Fuse EDA AI system, designed to automate complex, multi-step semiconductor design tasks. The companies are targeting improvements in design rule check (DRC) fixing and physical verification, leveraging Siemens’ Calibre and Aprisa tools.
“Our continued collaboration with TSMC exemplifies Siemens’ commitment to delivering AI-driven automation and advanced semiconductor design capabilities that accelerate our customers’ ability to innovate at the most advanced process nodes,” said Ankur Gupta. “By combining our AI innovations with TSMC’s leading-edge process technologies, we’re helping customers reach new levels of speed, accuracy and design confidence.”
TSMC emphasized the ecosystem angle of the partnership. “TSMC greatly values our longstanding partnership with Siemens… as we work together to enable next generation semiconductor designs,” said Aveek Sarkar.
Beyond AI, Siemens’ EDA tools have achieved certifications for TSMC’s latest process technologies, including 3nm, 2nm, A16, and A14 nodes. This ensures support for advanced digital, analog, RF, and memory designs, as well as reliability-aware simulations.
The collaboration also extends to 3D IC design using TSMC’s 3DFabric platform. Siemens’ Calibre tools support verification, thermal analysis, and interconnect validation for stacked chip designs — key capabilities as heterogeneous integration becomes mainstream.
In addition, the partnership covers silicon photonics via TSMC’s COUPE technology, signaling a broader push into next-generation chip architectures.
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