NEW DELHI, June 18, 2026 /PRNewswire/ -- Synergy Quantum today announced a portfolio of quantum-safe silicon IP cores for RISC-V-based system-on-chip designs, enabling semiconductor companies, processor developers and equipment manufacturers to integrate post-quantum cryptographic capabilities directly into ASICs, FPGAs and embedded platforms. Developed by Synergy Quantum, the IP portfolio combines post-quantum cryptographic acceleration with secure boot, hardware-bound identity, protected key handling, firmware verification and device-attestation capabilities.

The portfolio is designed for integration into RISC-V-based SoCs as dedicated security components, cryptographic coprocessors or building blocks within a broader hardware root-of-trust subsystem.By placing quantum-safe cryptographic functions directly in silicon, the architecture can improve performance, reduce dependence on software-only implementations and provide stronger isolation for sensitive keys and intermediate cryptographic values.

Bringing quantum-safe security into RISC-V silicon

RISC-V is increasingly being adopted across embedded systems, industrial platforms, communications infrastructure, defence electronics, automotive systems and custom semiconductor designs.Many of these devices are expected to remain operational for years or even decades. Their security architectures must therefore be capable of supporting the transition from classical cryptography to post-quantum security.

Synergy Quantum’s silicon IP portfolio is intended to help RISC-V developers address this transition at the processor and SoC level. Instead of treating post-quantum cryptography as an application-layer upgrade, the IP enables key establishment, signature verification, secure boot and device-trust operations to be implemented as dedicated hardware functions within the chip.The architecture supports industry-standard SoC interconnects and processor-extension interfaces, enabling the cores to be integrated with existing RISC-V processors and custom SoC architectures without requiring a complete redesign of the host platform.

Quantum-safe IP developed for hardware integration

The Synergy Quantum portfolio includes silicon IP and accelerator architectures supporting:

The IP can be configured according to the performance, power, silicon-area and security requirements of the target application.

Implementations can range from compact, low-power cryptographic blocks for embedded and IoT devices to higher-throughput accelerators for telecom, networking, data-centre and security-appliance applications.

A configurable RISC-V security architecture

The portfolio combines programmable RISC-V control with dedicated cryptographic hardware.

This model allows security policies, protocol handling and device-specific logic to be managed through software or firmware, while computationally intensive and security-sensitive operations are executed within isolated hardware datapaths.

The architecture can support:

The IP cores can be integrated individually or combined into a complete quantum-safe security subsystem.

This gives SoC developers the flexibility to adopt the capabilities required for a particular product while maintaining a path towards broader hardware-rooted security.

Designed for crypto agility

The post-quantum transition will continue to evolve as standards, implementation guidance and security research develop.

For semiconductor products with long deployment lifecycles, the ability to update cryptographic algorithms and policies is therefore essential.

Synergy Quantum’s architecture is designed to support crypto agility through reusable arithmetic engines, shared cryptographic datapaths and programmable security control.

Shared NTT and Keccak processing components can be used across multiple lattice-based cryptographic algorithms. This reduces unnecessary hardware duplication and allows multiple cryptographic functions to operate within a common silicon architecture.

Selected configurations can also support controlled cryptographic updates and hardware-enforced anti-rollback mechanisms, helping manufacturers respond to future changes without replacing the complete device architecture.

This enables a staged migration path from classical cryptography to hybrid implementations and ultimately to fully post-quantum operation.

Protection against implementation-level attacks

Mathematical resistance to quantum attacks is only one part of hardware security.

Physical implementations must also consider timing attacks, power analysis, electromagnetic analysis, fault injection and attempts to extract keys from memory or internal datapaths.

Synergy Quantum’s quantum-safe IP architecture includes options for:

These capabilities are designed for products that may operate in hostile, physically accessible or mission-critical environments.

Supporting semiconductor and system developers

The Synergy Quantum IP portfolio is intended for:

The cores can be integrated into secure processors, network controllers, communications equipment, gateways, firewalls, hardware-security platforms, industrial controllers, satellite systems and long-lifecycle connected devices.

Complementing the SynQ Silicon Trust Suite

The quantum-safe RISC-V silicon IP portfolio complements Synergy Quantum’s previously announced SynQ Silicon Trust Suite. The SynQ Silicon Trust Suite provides the broader system-level framework for secure boot, protected key custody, device identity, signing, attestation and security-policy enforcement. The RISC-V quantum-safe silicon IP cores provide the underlying semiconductor building blocks that can enable these capabilities inside custom processors and SoCs.

Together, the two offerings give Synergy Quantum a vertically integrated approach spanning:

This enables semiconductor developers to integrate quantum-safe hardware capabilities directly into their chips, while equipment manufacturers and infrastructure operators can deploy a broader end-to-end trust architecture through the SynQ Silicon Trust Suite.

“RISC-V gives semiconductor developers the flexibility to build processors and systems around their own requirements. Quantum-safe security must become part of that flexibility and must be available as a native silicon capability rather than an afterthought added at the software layer. Synergy Quantum’s quantum-safe silicon IP cores are designed to help RISC-V developers integrate post-quantum cryptography, secure boot, device identity and hardware-rooted trust directly into the SoC architecture.” - Jay Oberai, Founder, Synergy Quantum

Enabling sovereign quantum-safe semiconductor development

Ownership and control of cryptographic silicon IP are increasingly important for governments, defence organisations, critical-infrastructure operators and semiconductor manufacturers. Synergy Quantum’s development of quantum-safe IP for RISC-V-based systems provides a foundation for locally controlled processors, secure controllers, communications devices and mission platforms.

The use of configurable and auditable RISC-V architectures also enables developers to customise security subsystems according to national, sectoral and product-specific requirements.This can reduce dependence on fixed external cryptographic components while providing greater control over algorithm selection, security policies and cryptographic lifecycle management.

About Synergy Quantum

Synergy Quantum develops quantum-secure platforms, cryptographic hardware and semiconductor security IP for governments, semiconductor companies, regulated enterprises and critical-infrastructure operators.Its work spans post-quantum cryptography, RISC-V-integrated quantum-safe IP, hardware roots of trust, cryptographic acceleration, quantum-secure connectivity and crypto-agile infrastructure.The company’s mission is to protect the data, devices and networks that power modern civilisation and to build the trusted hardware foundation required for the post-quantum era.

For more information, visit synergyquantum.in

“This is a company press release that is not part of editorial content. No journalist of The Hindu businessline was involved in the publication of this release.”

Published on June 19, 2026