




















Huawei expects the architecture to evolve significantly over the next decade, with plans to move from “local critical path folding to full-scale and multiplayer-folding for full-stack optimisation from devices to systems”.
Chinese technology company Huawei Technologies has introduced a new semiconductor scaling framework and chip architecture that it says could power processors equivalent to 1.4-nanometre technology by 2031, as the company intensifies efforts to build a fully independent chip ecosystem amid ongoing US sanctions.
The announcement was made during the 2026 IEEE International Symposium on Circuits and Systems (ISCAS) in Shanghai by He Tingbo, chair of Huawei’s Scientist Committee and president of the company’s semiconductor business unit.
Must read: Why Japan's semiconductor consolidation is a wake-up call for India's chip ambitions
At the centre of Huawei’s roadmap is a new principle called the Tau Scaling Law, which the company says moves beyond the semiconductor industry’s traditional dependence on transistor miniaturisation under Moore’s Law.
Instead of relying purely on shrinking transistor dimensions, Huawei’s framework focuses on “time scaling” to improve chip performance and transistor density.
He said Huawei has already applied the framework across 381 chips that have been designed and mass produced over the past six years.
Huawei also unveiled a new chip design approach called LogicFolding architecture, which it claims can lower resistance and capacitance during signal transmission, improving chip efficiency and transistor density.
According to the company, its next-generation Kirin processors launching later this year will be the first commercial chips to adopt the LogicFolding architecture.
Must read: Tata Electronics-ASML tie-up signals India’s semiconductor ambitions are moving beyond assembly
“Before winter 2026, we will bring the surprise … [a] big leap ahead,” He said during her keynote address.
The executive said Huawei spent six years building domestic semiconductor capabilities, including electronic design automation (EDA) tools and chip design methodologies, as China pushes to reduce reliance on foreign technologies.
“I used to think it may take us 10 years, but six years we are here,” He said.
Huawei expects the architecture to evolve significantly over the next decade, with plans to move from “local critical path folding to full-scale and multiplayer-folding for full-stack optimisation from devices to systems”.
“From 2026 to 2035, as a wide range of R&D explorations goes into products, the transistor density will rise, operating frequency will surge and we keep delivering cutting edge mobile chips to the market,” He added.
Must read: From textiles to chips: Suchi Semicon targets 3 million packaged chips daily after ISM approval
The company also projected confidence in its AI chip ambitions as it expands its challenge to global semiconductor players.
“The performance of our new chip can fully compete with the local counterparts. For AI systems, we remain equally confident of delivering high quality, low latency large-scale solutions,” He said.
For Unparalleled coverage of India's Businesses and Economy – Subscribe to Business Today Magazine
Published on: May 25, 2026 12:03 PM IST
此内容由惯性聚合(RSS阅读器)自动聚合整理,仅供阅读参考。 原文来自 — 版权归原作者所有。