It has been nine years since a Chinese HPC supercomputer was at the top of the High Performance Linpack performance rankings, but as we all know, China did break through the exascale flops barrier at 64-bit precision before the United States did – and on two different systems. China didn’t brag about it, but let enough information leak out to US experts so the word would get out.

To be specific, the Sunway OceanLight machine installed at NSC Qingdao came first, which we initially talked about in February 2021 and then did a deep dive on the system’s architecture in March 2022. I think the full OceanLight system, based on the Sunway SW26010-Pro CPU and with 41.93 million cores, had a peak theoretical performance and hit 1.22 petaflops on HPL, is rumored to have been up and running in March 2021.

The Tianhe-3 supercomputer based on a hybrid Phytium 2000 Arm processor and the Matrix 3000 DSP co-processor, which had a peak theoretical performance of around 2.05 exaflops and delivered maybe 1.57 exaflops on HPL, was fired up initially at NSC Guangzhou at lower performance numbers in October 2021. This was not the full and was apparently fully fleshed out in December 2023 at the numbers we cite. But in late 2021, using older Matrix 2000+ DSP coprocessors, the Tianhe-3 prototype still weighed in at 1.3 exaflops on HPL against 1.7 exaflops peak.

This beat out Oak Ridge’s “Frontier” hybrid AMD “Trento” Epyc CPU paired with four AMD “Aldebaran” MI250X GPU accelerators, which had just under 8.7 million cores across those compute engines and which was rated at 1.19 exaflops on HPL and 1.68 exaflops peak. The Frontier system was accepted and put into production in May 2022.

China beat this date and this performance by more than a year, and using older process technologies, running hot, taking up a lot of space, and presumably high cost even if the compute engines are hanging back on chip manufacturing processes because China has no choice if it is going to use its indigenous Semiconductor Manufacturing International Corp (SMIC) foundry. These machines were expensive, but if you want to design airframes for travel and war, and nuclear weapons, then you can’t wait around for the United States to stop embargoing Nvidia and AMD GPUs or other compute engines and maybe networking. China wants to – and can easily afford to and has the will to – stand on its own two feet.

The same approach was taken with the new number one ranked machine on the Top500 supercomputer rankings – the “LineShine” supercomputer installed at NSC Shenzhen in China. But all of the technologies used to make LineShine have advanced by five years and that is why this system is not only bigger, but is arguably better than its OceanLight and Tianhe-3 predecessors.

LineShine is based on an Armv9.2 CPU core that has SVE2 vector units and the relatively new SME matrix math units as well as integer processing units, and in this sense this is like Intel P-Core Xeon processors that have integer processing as well as AVX vector units and AMX matrix units. To one way of thinking about it, the LX2 and modern Xeon P-core compute engines are a kind of hybrid CPU-GPU complex with the graphics capabilities stripped out.

The LX2 chip was designed by NSC Shenzhen in conjunction with Chinese IT giant Huawei (presumably its HiSilicon chip division). The LingKun LX2 CPU design has 304 active cores in a socket, and very likely there are more cores on the chip to increase the yield. The LineShine machine has a proprietary LingQi LQLink interconnect, which I am reasonably sure is based on a variation of InfiniBand technology but it could be a jacked-up and stripped-down version of Ethernet.

This LX2 CPU delivers enough FP64 oomph with its SVE2 and SME math units that it only takes 13.79 million cores to deliver a peak theoretical performance of 2.74 exaflops (rounding to three significant digits). That is 32.9 percent fewer cores than the OceanLight CPU, which also was a hybrid CPU-vector-matrix design, to deliver 46.7 percent more performance. On the HPL test, LineShine delivers just a tad under 2.2 exaflops of oomph and that makes it 21.5 percent more powerful than the former top ranked machine, the “El Capitan” supercomputer based on AMD MI300A compute engines located at Lawrence Livermore National Laboratory in the United States. China no doubt wanted to top El Capitan, but more importantly, it wanted to top OceanLight and Tianhe-3 machines.

Let’s take a deeper dive into this LineShine machine, which we wish had been nicknamed “Sunbeam” because that is what it sounds like.

NSC Shenzhen put out a paper called Breaking the Training Barrier of Billion-Parameter Universal Machine Learning Interatomic Potentials on April 17 that included some basic descriptions of the LineShine machine, which we riffed on above. Some more details were made available in a presentation that Yutong Lu, the main architect of the supercomputer, made at the second annual International Forum for HPC and AI Co-Driven Innovation (HACI 2026), which was held in Shenzhen from May 22 to May 25. The presentation for LineShine was not made public, but Torsten Hoefler, the chief architect for AI and machine learning at CSCS in Switzerland as well as a professor at ETH Zurich, posted a few slides from the event. Tadashi Ogawa, a researcher for many labs in Japan who is now technical sales manager for Panasas for the Land of the Rising Sun, did as well.

These posts give us a lot more insight into LineShine than that paper, which also mentioned a another exascale-class supercomputer called China New-generation Intelligent Supercomputer (CNIS), which is based on nodes using a pair of undisclosed 64-bit CPUs and eight GPUs of unknown origin. Presumably this is based on indigenous compute engines as well. Here is what the paper says about this CNIS machine, which has 5,632 nodes:

“The host processor runs at 2.4 GHz with 64 cores in a NUMA architecture, connected to 8-channel DDR5-6400 memory and PCIe Gen5 interfaces, delivering 64 GB/s host-to-device bandwidth. Each GPGPU provides 32.7 TFLOPS (FP64), 65.5 TFLOPS (FP32), and 470 TFLOPS (FP16) peak performance, with 64 GB HBM (1.8 TB/sec bandwidth), 320 SIMD units, 768 KB registers, 64 KB LDS, and 8 MB L2 cache. The accelerators are interconnected via high-speed chip-to-chip links, while nodes are connected through a proprietary InfiniBand-like RDMA network with a three-layer Clos dual-plane topology, providing 4×400 Gb/sec per node.”

But we are focusing on LineShine here. Here is the block diagram and the specs for the LX2 compute engine:

As you can see, there are two chiplets interlinked in the LX2 design. There are 48 core blocks in each chiplet, and I think there are four cores in each of those blocks. That yields 192 raw cores per chiplet and 384 cores per socket, which is a lot but not entirely crazy. That 304 cores that are exposed is due to yield, and at 79.2 percent core yield, that is about what we expect from the SMIC foundry. We think it is highly likely that these LX2 chiplets are etched using SMIC 7 nanometer processes at the N+3 refinement, and we base that on the fact that the chip only runs at 1.55 GHz.

That is nowhere near the 3 GHz that SMIC can push with that process, but it is probably lower to get the memory and core speeds more balanced. You want memory running a lot faster than cores, which is something I have argued for, especially when cranking the core clocks raises the power consumption as you exponentially go up. As it is, at a relatively slow 1.55 GHz, which is slower than a lot of GPUs, but not by much, the LX2 complex is burning 690 watts, which is fairly high. NSC Shenzhen clearly slowed the chip down to get into a thermal sweet spot and made it up in volume for the supercomputer, thus boosting performance per watt on massively scaled HPC and AI workloads.

This is a good tradeoff, no matter what the GPU crowd might tell you. And it is one you have to make if you are stuck at 7 nanometers.

The paper says the LX2 has eight HBM stacks, but clearly it has sixteen and they meant to say eight stacks per chiplet. Each HBM stack is allocated to a block of 24 LX2 cores on each chiplet, and despite what the paper says, it has to be 32 GB of memory and 4 TB/sec of bandwidth per chiplet, for a total of 64 GB of HBM per socket at 8 TB/sec. If this is the case, then it is probably a slightly goosed variant of HBM2E memory.

As for DRAM memory, which the LX2 supports as well, we don’t know the capacity but we do know that NSC Shenzhen is using a 3D stacking with custom DRAM logic wafers to put them on the LX2 package. Where and how is not clear, but I strongly suspect that this DRAM is made using LPDDR5X memory that  ChangXin Memory Technologies was showing off late last year running at 10.7 GHz. But that’s just a hunch. We do know that each socket has 256 GB of DRAM in addition to the 64 GB of HBM memory. This DRAM memory is organized into eight NUMA domains across the two compute chiplets, and a SDMA engine automagically manages the movement of data between the two types of memory.

As you can see on the right side of the chart above, there are eight DRAM tiles and four I/O dies that are stacked on top of the core tiles, with an interconnect that links them together and to the core package at the left and right side, shown in the dark blue IP blocks.

The exploded view on the chart above shows the SME and SVE2 units, and as you can see, the SME unit is a 2D matrix grid that accumulates to what we presume is an FP32 register. This appears to be a custom implementation by Huawei of the SME design. The SVE2 units seem to be block copied from Neoverse IP.

Here are some specs on the SME unit and tweaks to the HBM/LPDDR5X memory:

Speaking broadly – too broadly, really – the AI paper describing the LX2 chip says that it supports FP64/FP32/FP16/INT8 via SME and SVE units, delivering up to 60.3 teraflops at FP64 precision and 120.6 teraflops at FP32 precision. That does not tell us if this is on the SME or SVE units, and it does not tell us what the lower precision FP16 and INT8 performance is, which might help us figure this out.

Here is how the LineShine system is stacked up:

Each LineShine node is a two-socket LX2 server, which is an interesting choice. A LineShine blade has eight of these two-socket nodes on it, and a LineShine frame puts sixteen of these blades into a box that uses PCI-Express 5.0 connectivity to lash the nodes on a blade together and uses switches to link the sixteen blades to each other inside the frame. (That is the inexpensive way to do it.) That would yield a compute domain of 256 LX2 CPUs.

A LineShine cabinet has two of these blade servers, which NSC Shenzhen calls a frame, and it is rated at 30.87 petaflops at FP64 precision.

To scale out further, the frames use a proprietary interconnect, which we are fairly certain is an Ethernet variant but it could be a derivative of InfiniBand, called LingQi. This interconnect is implemented in a dual-plane, multi-rail, fat-tree topology, offering 1.6 Tb/sec of bandwidth per node. (That’s two ports running at 400 Gb/sec each on a network interface card that is implemented inside the LX2 compute engine package.)

The LingQi interconnect is comprised of a four-layer fat tree, and a single hop latency across the network is 1.07 microseconds. (This sounds more like Ethernet than InfiniBand. But it might just be an honest assessment of InfiniBand’s latency in the field.) The full bi-section bandwidth across the LingQi network is more than 3.5 Pb/sec. it looks like LingQi is the Layer 1 of the switch fabric inside the LineShine frames, with Layer 2 cross-coupling the blades and talking up to a Layer 3 aggregation layer. These are all copper connections, which is important. To cross link all of the 184 frames in the LineShine system together, there are optical links going up to Layer 4 of the LingQi network, which is implemented with 32 network frames.

The full LineShine machine has 20,480 LX2 nodes, according to the AI paper published by NSC Shenzhen, and that works out to 12,451,840 cores. But the LineShine configuration used to run the High Performance Linpack benchmark to get its number one ranking on the Top500 list for June, had 13,789,440 cores. That is an extra 2,200 nodes, for a total of 22,680 nodes. There is little doubt that China can scale LineShine further if it wants or needs to.

The LineShine machine has a computational efficiency of 80.35 percent, which is pretty damned good and speaks to the efficiencies of merging big math with a healthy core instead of separating them. As a point of reference, the K supercomputer built by Fujitsu for RIKEN Lab in Japan set the high watermark for computational efficiency at 93 percent running HPL, and its follow-on “Fugaku” system running for the past few years has a computational efficiency of 82.3 percent.

The LineShine system tested burns 42.2 megawatts of power, which is considerably more than the less than 30 megawatts used by the big three exascale-class machines in the United States – Oak Ridge’s “Frontier” system, Lawrence Livermore’s “El Capitan” system, and Argonne’s “Aurora” system. But that extra power comes with less computational complexity because there is no offload model and the LX2 has a unified HBM and DRAM memory space as well. There is no GPU software cost, either, which is buried in the hardware costs of Nvidia and AMD GPUs no matter how much these two chip makers protest otherwise.

I can assure you, nothing is free in this world, and this is particularly true of AI and HPC software stacks.

The main thing is that China wants to be independent and the policies of the US government are forcing it to be. And LineShine is just the latest – and best – expression of that independence. And as we have contended from the beginning, for GenAI workloads, a lot of inference will be done on CPUs with beefy vector and matrix units and a mix of fat and fast memory. This will be particularly true of a lot of agentic AI workloads. And the LX2 processor, like IBM’s Power 10 and Power 11 processors as well as its z16 and z17 CPUs and Intel’s Xeon 6 P-core, is ready for that world. Other CPUs currently out are not.