Interest in RISC-V has grown rapidly over the last few years. While many use cases have been deeply embedded, during 2026 we expect to see a rapid increase in the number of chips and boards available to developers that support Linux. In this blog I will look at some of the drivers for this growth, the value proposition of RISC-V and explain why supporting RISC-V is important to Canonical.
RISC-V is an open standard instruction set architecture (ISA). An ISA describes the set of instructions that a CPU executes to run a program. Other examples of modern ISAs include Armv8-A or Intel x86_64. RISC-V was created in 2010, and RISC-V International was founded in 2015 to act as a steward for the specification(s). These are developed through community engagement with industry, academia, and even enthusiastic individuals.
As an open standard, anyone can create a RISC-V CPU. As a specification it provides foundational technology standards, while allowing innovation both through extensions to the ISA, and also in terms of business models. It is not an implementation of a CPU, but an architecture specification like USB or Ethernet.
Today, RISC-V is widely used and shipping in volume. Most uses of RISC-V have been deeply embedded – which means they are tied to the product they are part of and not available to individual developers, but that situation is changing and improving. During 2026 we expect to see multiple vendors with development boards supporting the RVA23 profile that can run Linux.
There are many reasons to consider using RISC-V, from the philosophy of adopting an open standard architecture, to concerns over technology sovereignty. There are also fundamental business and technology drivers which I will explain in more detail.
As a permissively licensed ISA, RISC-V offers the ultimate flexibility for businesses and the open source community. Implementations of RISC-V can be open source, closed source, licensed as IP, or developed for private in-house use.
There are many companies offering RISC-V CPUs as commercial IP, and companies such as Qualcomm and NVIDIA use RISC-V cores within their products.
One strong endorsement of RISC-V has been from Google through the OpenTitan project, where a fully open source CPU is being used as a security root of trust. Google recently announced shipping production silicon in Chromebooks and use in their data centers.
Unlike most other ISAs, the RISC-V ISA has been specifically designed to be extensible, and is also split into multiple sets of extensions that you can pick and choose from. This gives user more choice and power in using the ISA for their projects; for example, one could use this ISA to:
With fields like AI/ML progressing ever more rapidly, having a hardware architecture that allows innovation and experimentation becomes increasingly important. While this flexibility could cause problems for the software ecosystem, RISC-V has multiple ways to manage this, from grouping subsets of instructions together (such as ‘F’ for floating point instructions) to profiles, such as RVA23 which groups together multiple sets of instructions. Furthermore for many deeply embedded use cases, where the developer controls both software and hardware, this is less of a concern.
A common question from people new to RISC-V is “while the hardware side sounds really interesting, how can I be confident my applications will run on it?”. This can be answered in a number of ways, and a future blog will look at the specifics around supporting custom instructions in Ubuntu. However, the short version is that the open source community has already widely adopted RISC-V and provides excellent support for it in many parts of the ecosystem. This includes the Linux kernel, toolchains such as GCC and LLVM and most real-time operating systems too, while Ubuntu has supported RISC-V since 2021.
The standardization efforts around profiles ensure compatibility between different implementations – for example, RVA23-compliant software is portable across any RVA23 hardware.
From Canonical’s perspective, we want to support the ISAs that our community and customers want to use. Wherever open source ports to RISC-V exist, we will try to support them, and provide the same standard of support as other architectures. That means Long Term Support (LTS) versions of Ubuntu will support RISC-V for up to 15 years with a subscription to Ubuntu Pro with legacy support. Ubuntu 24.04 LTS supports the RVA20 profile while from 25.10 onwards (including 26.04 LTS) we will support RVA23. Explaining profiles is a topic for a future blog, but for now suffice to say that most Linux-capable RISC-V hardware will be supported by us for many years to come.
Beyond the generic support Canonical offers at the profile level, we also work with silicon partners to provide specific support for their products. These packages can be accessed on our website. Please note Partner RISC-V builds that are built and hosted by our partners do not benefit from Canonical’s ongoing support programs.
Explore Canonical-supported RISC-V builds>
Explore partner RISC-V builds >
We also provide a cookbook for vendors to help them build their own Ubuntu images.
Our launchpad website provides builds of all the packages in our repo. Vendors can also use launchpad to host their own private packages, for example to include custom instructions.
Explore the Ubuntu 25.10 RISC-V repository
RISC-V is disrupting the semiconductor industry and enabling new applications and use cases for custom silicon. While much of the focus has been on hardware, the software community is also very active in developing support for RISC-V and it is already at a good level of maturity. Canonical treats RISC-V as a first-class citizen and our goal is to support it to the same level as competing architectures. We are already well on the way to this goal.
If you are considering using RISC-V in your next project, from Ubuntu Core for IoT and edge devices to Ubuntu Pro and Ubuntu Server, then we’ve got you covered. Why not talk to us about your requirements?
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