Researchers at the National University of Singapore and Applied Materials have developed a method to grow extremely thin films on chips. 

Interestingly, the tungsten disulfide film is only 0.7 nanometers thick, protecting the tiny copper wires inside microchips.

Atomically thin material

We are building a digital world of roaring AI models and fast supercomputers, but the physical wires carrying that data are choking.

Computer chips are shrinking toward their absolute physical limits, leaving the microscopic copper wires inside them with virtually no breathing room.

The issue isn’t actually the copper itself. It is the bulky insulation wrapped around it.

Every nanoscale copper wire inside a modern processor requires two bodyguard layers. A barrier layer keeps runaway copper atoms from leaking out and short-circuiting the chip. Meanwhile, a liner layer acts as a structural glue, ensuring the copper sticks smoothly to the chip’s foundation. 

Today, the tech industry uses tantalum-based materials for these coatings. But these are hard to scale down.

Yet as chip components shrink, these bulky coatings consume half the wire’s cross-section, spiking electrical resistance and choking chip performance.

To solve this, researchers have successfully grown an ultrathin film of tungsten disulfide that acts as both a liner and a barrier.

And its total thickness is just 0.7 nanometers. 

Reduces electrical resistance

Conventional engineering logic dictated that you needed two entirely separate materials to handle the dual jobs of adhesion and insulation. How does a single layer of atoms replace a bulky, multi-material stack? It happens through an intentional structural labyrinth.

Using advanced computational modeling, the NUS Department of Chemistry discovered that the tungsten disulfide (WS2) film grows in a chaotic, polycrystalline pattern. It is made of tiny, microscopic grains. When layered, these grains are completely mismatched.

“The calculations showed us that the polycrystalline nature of these films, which might initially seem like a limitation compared with a perfect single crystal, is actually an asset. The random grain orientations between layers create a labyrinth that copper atoms struggle to traverse,” said Professor Richard Wong from the NUS Department of Chemistry, who is also a co-director of the Corporate Lab.

“This gives us a design principle where we engineer the grain structure to optimize barrier performance instead of pursuing perfect crystallinity,” Wong added. 

This random alignment creates a winding, staggered barrier rather than a straight path. As a result, the overlapping boundaries trap copper atoms in a structural labyrinth, blocking them from leaking through.

When tested under heavy-duty processing demands, the WS2 atomic shield delivered definitive results. It slashed electrical resistance by a millionfold, leaving a 20-nanometer wire’s space wide open for copper current by shrinking the coating’s footprint to just 7 percent. 

Plus, the method extended the projected lifespan of the wiring by more than 10 times under extreme electrical stress.

Plasma-free process

Designed for immediate commercial viability, the team’s plasma-free growth process operates at a low 350°C (662°F) to prevent damage to underlying chip components. 

This method is the first to simultaneously meet all four strict industry manufacturing standards: low-temperature execution, uniform coverage across full wafers, atomic-level thickness control, and over 95 percent conformal coating inside deep, narrow trenches.

With global chip demand hurtling toward US$1 trillion annually, this atom-thin shield arrives just in time. The team notes the new material is thinner than any barrier target set on the international semiconductor technology roadmap through 2037.

The findings were published in the journal Nature Electronics.

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