SK hynix has launched iHBM, an architecture featuring a Dynamic Random Access Memory (DRAM) stack with embedded Integrated Cooling Elements (ICEs). These cooling elements provide an additional heat dissipation pathway from the high-bandwidth memory (HBM) package. The ICEs are made of electrically non-conductive, thermally conductive silicon-based material.

Kangwook Lee, Senior Vice President and Head of Packaging Development at SK hynix said “iHBM is an optimal solution for thermal management, combining our memory design capabilities with advanced packaging technology”.

The thermal management problem

An HBM is a memory chip in which multiple DRAM dies are stacked vertically in a 3D layout. This shortens interconnect lengths, increase data speeds, reduce latency, and lower power consumption. Because of these benefits HBMs are heavily used in AI servers. The technology has evolved through successive generations from HBM, HBM2, HBM2E, HBM3, HBM3E, to HBM4.

For meeting the surging AI data processing demand, HBM technology is moving towards higher stacking and faster speeds. These two factors are also increasing the thermal load on the HBM package.

Moreover the key driver defining the competitiveness of next-generation HBM chips is the management of the thermal power density at an interface connecting HBM and the Graphic Processing Unit (GPU) also known as the Die-to-Die Physical Layer (D2D PHY). It is also a region with the highest heat concentration.

Architecture and integration

With the iHBM solution, SK hynix has taken a structural approach to addressing the thermal management problem. The existing HBM products rely on an indirect cooling method that draws heat away through the core die, whereas the iHBM solution places ICEs on top of the D2D PHY region. This creates an additional heat dissipation pathway to reduce the thermal load.

This heat management solution helps to reduce thermal resistance by 30 percent and enables chips to operate stably even in high-temperature and high-pressure conditions.

Industrial scale production

The company states that it has mass-production capabilities to enable stable high-volume production of iHBM-equipped chips (which are likely to be fabricated at its Cheongju M15X fab). These will utilize SK hynix`s Wafer Level Packaging (WLP) process based on Mass Reflow Molded Underfill (MR-MUF) technology. MR-MUF process enables stacking semiconductors by injecting liquid protective materials between chips.

The iHBM solution also offers high design compatibility with existing System-in-Package (SiP) architectures, allowing adoption to this new thermal management technology with minimal design adjustments.

The iHBM is, slated for deployment in next-generation HBM products, like the upcoming HBM5. With this product SK hynix aims to increase the stability and operational efficiency of AI data centers by meeting heat management standards required in high-density and high-bandwidth environments.

Future developments

SK hynix holds a dominant competitive position in HBM segment. It has also initiated proactive R&D in next-generation high-bandwidth storage technologies like High Bandwidth Flash (HBF) and Processing-In-Memory (PIM).

HBF is an emerging memory tier positioned between HBM and Solid-State Drive (SSD). It combines HBM class bandwidth characteristics with the high-density capacity of NAND flash-based storage, and is designed to improve scalability and power efficiency across AI infrastructure.

PIM is a next-generation memory architecture that integrates processing logic directly into the memory die, eliminating the traditional von Neumann bottleneck between memory and processor thereby dramatically improving bandwidth efficiency and energy consumption.

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