KAIST researchers have developed a simulation-based method to predict how small future transistors can become before quantum effects begin to interfere with their operation, a breakthrough that could help engineers design next-generation semiconductor chips more efficiently.

The team used atom-level quantum mechanical calculations to identify the scaling limits of transistors, the tiny switches that control the flow of electricity in electronic devices. The findings could help chipmakers continue shrinking transistors beyond current technology nodes while reducing costly trial-and-error during development.

As the semiconductor industry enters the so-called 2 nm era, the physical dimensions of transistors remain significantly larger than 2 nanometers. One of the biggest obstacles to further miniaturization is quantum tunneling, a phenomenon in which electrons leak through barriers that would normally block them, making it difficult to control current flow.

Understanding where that limit lies has been challenging because it is nearly impossible to directly measure the atomic-scale interactions occurring where metal contacts connect to semiconductor channels.

Chasing atomic limits

To overcome that challenge, the KAIST team relied on first-principles calculations, a computational approach that predicts material behavior using the laws of physics rather than experimental data.

Building on a previously developed framework known as multi-space constrained-search density functional theory (MS-DFT), the researchers conducted virtual transfer length method experiments, a standard technique used to measure contact resistance between metal electrodes and semiconductor materials.

The simulations allowed the team to examine how electrons move across metal-semiconductor interfaces and determine the critical tunneling length, the point at which electron leakage begins to affect transistor performance.

The researchers applied the method to monolayer molybdenum disulfide (MoS2), a two-dimensional semiconductor considered a promising candidate for future transistor channels because it can be manufactured at atomic-layer thickness.

Their analysis showed that electron penetration into the channel varies depending on the choice of metal electrode and the atomic structure of the contact interface. As a result, the minimum achievable transistor size is not fixed but depends on material selection and device design.

Beyond today’s nodes

According to the study, the critical tunneling length changes based on the work function of the metal and the geometry of the contact structure. This means engineers can potentially tune transistor scaling limits by selecting different materials and interface configurations.

Among the combinations studied, the team found that electron leakage could be suppressed at dimensions below 4 nanometers, suggesting future transistors may be scaled even further than current technologies allow.

The researchers also proposed a design strategy that combines two-dimensional semiconductors with different properties to reduce power consumption in future chips.

“This study is significant because it presents a new physical criterion for defining how small next-generation transistors can become,” said Professor Yong-Hoon Kim.

“By computationally analyzing quantum mechanical phenomena in the sub-10 nm regime, which are difficult to probe experimentally, we have opened a path toward utilizing these findings in next-generation transistor design.”

The team believes the approach could provide chip designers with a platform for predicting transistor performance and scaling limits before fabrication begins, potentially shortening development cycles for future AI and high-performance computing chips.

The study was published in the journal npj Computational Materials.

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