IBM has introduced what it calls the world’s first sub-1 nanometer semiconductor technology, unveiling a 0.7 nm chip built on a new three-dimensional transistor architecture designed to extend chip scaling beyond current limits.

The company said the chip packs nearly 100 billion transistors onto a device roughly the size of a fingernail, almost doubling the transistor density of IBM’s 2 nm chip announced in 2021.

According to IBM, the new technology could deliver up to 50 percent higher performance or 70 percent better energy efficiency than its 2 nm node chips, potentially benefiting artificial intelligence systems, cloud infrastructure, and future consumer electronics.

The breakthrough comes as the semiconductor industry faces growing challenges in shrinking transistor sizes using conventional designs. IBM said the new architecture provides a path for continued scaling even as chip features approach atomic dimensions.

Beyond traditional scaling

At the heart of the development is a new transistor design called “nanostack,” which IBM describes as the industry’s first known three-dimensional nanosheet-based architecture.

Unlike conventional transistor layouts, nanostack vertically stacks and staggers transistors, allowing more components to be integrated within the same footprint. The design also enables different materials to be used in separate layers, helping engineers optimize performance and power consumption independently.

“IBM’s latest chip breakthrough marks a landmark moment in computing, pushing technology beyond the nanometer era to the scale of atoms. With our new nanostack architecture, we’re not just making smaller transistors, we’re reinventing how chips are built to deliver dramatically more power and energy efficiency,” said Jay Gambetta, Director of IBM Research and IBM Fellow.

IBM said researchers experimentally validated the architecture through ultra-thin dielectric bonding in CMOS integration, dual-channel engineering demonstrations, and functional CMOS inverter operation. The company said these tests confirmed that the structure can be physically manufactured and perform computing functions.

The technology also showed improvements in memory scaling. IBM researchers reported a 40 percent reduction in SRAM cell size, which could help chipmakers build denser and more efficient processors while supporting the growing memory demands of AI workloads.

Roadmap extends decade

IBM believes the nanostack design could support semiconductor scaling for at least another decade.

The company noted that transistor node names no longer represent exact physical dimensions but instead identify manufacturing generations. Nevertheless, IBM’s 0.7 nm, or 7-angstrom, technology demonstrates that further miniaturization remains possible below the 1 nm threshold.

The work is being carried out at IBM’s semiconductor research facility in Albany, New York. The site is expected to house a High Numerical Aperture Extreme Ultraviolet (High NA EUV) lithography system from ASML, a tool considered critical for future chip manufacturing.

IBM said it has been collaborating with Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions on High NA EUV process development and has already produced working devices using the technology.

The company expects the earliest commercial adoption of nanostack-based chips could occur within the next five years.

The latest results were presented at the VLSI 2026 Symposium.

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