Rising workloads from AI systems and large language models are pushing current chip architectures to their limits, forcing the industry to look beyond conventional silicon scaling. For decades, Moore’s Law guided progress by predicting a steady doubling of computing power roughly every two years. 

However, as transistor dimensions approach atomic scales, quantum effects, heat dissipation, and fabrication constraints are making further miniaturization increasingly difficult. In response, researchers are turning to alternative materials and architectures. 

Among them, two-dimensional (2D) semiconductors are gaining traction as a promising post-Moore pathway, offering atomically thin structures that could enable continued transistor scaling while improving energy efficiency and performance.

Doping advances reveal critical weakness in 2D chip materials 

Controlling electrical behavior in atomically thin materials relies on precise chemical tuning, where small amounts of foreign atoms are introduced to modify conductivity – a process known as doping. This enables the creation of n-type (electron-rich) and p-type (hole-rich) semiconductors, both essential for modern electronics. 

While n-type 2D materials such as molybdenum disulphide and molybdenum diselenide are already well established, achieving high-performance and stable p-type counterparts remains a significant challenge, limiting the full realization of 2D semiconductor-based devices, the South China Morning Post writes.

Modern transistor architectures depend on the complementary pairing of n-type and p-type materials, making the shortage of high-performance p-type options a major constraint for next-generation chip design. This limitation is becoming especially acute as the industry explores sub-5-nanometer nodes in two-dimensional semiconductor systems, where material balance is critical for reliable device operation.

To tackle this issue, a research team led by Zhu Mengjian, alongside Ren Wencai and Xu Chuan from the Institute of Metal Research, developed a new method for preparing 2D semiconductors. Their work outlines an approach aimed at overcoming current material constraints and advancing the practical development of 2D chip technologies.

Gold-based substrate drives rapid scaling of 2D semiconductors 

A redesigned growth approach is significantly accelerating how 2D semiconductor materials can be produced at scale. The research team reengineered the chemical vapour deposition (CVD) technique by introducing a liquid gold/tungsten bilayer as the substrate. This enabled wafer-scale growth of monolayer tungsten silicon nitride films with tunable doping properties.

The method expands single-crystal domains to sub-millimeter sizes and dramatically improves production speed – from rates as low as roughly 0.00004 inches over five hours to about 0.0008 inches per minute, representing an increase of around 1,000 times. The resulting films reached dimensions of approximately 1.4 by 0.7 inches, marking a substantial step toward scalable manufacturing of high-performance 2D semiconductor materials.

From a device-performance standpoint, monolayer tungsten silicon nitride combines several key advantages, including strong hole mobility and high on-state current density, alongside robust mechanical strength, efficient heat dissipation, and solid chemical stability. These properties make it a promising candidate for advanced transistor design.

With the ability to produce larger-area films and control doping more precisely, the new method could help move 2D semiconductors closer to real-world manufacturing. In particular, it supports the scalable integration of these materials into CMOS architectures, a critical step toward their adoption in next-generation chip technologies.