The JEDEC Solid State Technology Association has officially detailed the preliminary specifications for the LPDDR6 memory standard. Designed to succeed LPDDR5 and LPDDR5X, this new architecture introduces significant structural changes aimed at meeting the high data demands of next-generation artificial intelligence (AI) and server applications.

Processing-in-Memory (PIM) Technology

The most significant innovation in the LPDDR6 standard is the implementation of Processing-in-Memory (PIM). This architecture allows the RAM chip to perform specific computational tasks internally rather than constantly offloading them to the central processor. By minimizing the continuous transfer of data across the motherboard, PIM simultaneously increases system speed and substantially reduces power consumption.

Physical and Architectural Advancements

To support these performance gains, the hardware has undergone several physical modifications:

• Expanded Bus Width: The internal communication bus has been upgraded from 16 to 24 sub-channels. This expansion allows for higher chip density within a single module, resulting in greater capacity without increasing the physical footprint.

• SOCAMM2 Form Factor: The standard introduces the SOCAMM2 (Solderless Compression Attached Memory Module) connector. This more compact format simplifies maintenance and facilitates upgrades for devices transitioning from previous generations.

LPDDR6 is engineered to reach capacities of up to 512 GB, providing the necessary bandwidth for data-intensive tasks. According to JEDEC Chairman Mian Quddus, the organization is currently finalizing technical details before the official publication of the standard.

Industry leaders are already preparing for this transition. SK Hynix has projected a 33% speed increase for mobile devices, while Samsung and Qualcomm are reportedly developing LPDDR6X variants capable of reaching 1 TB capacities and speeds of 14.4 Gbps. The initial rollout is expected to target the next generation of AI servers, where power efficiency and data throughput are most critical. Manufacturers will also gain greater flexibility in configuring memory to balance speed and data integrity for specific consumer products.