Alibaba delivers RISC-V server chip optimized to run China’s top AI models
Claims its set performance records but looks to be years behind western fare
Alibaba has revealed a new server chip that it says is the most powerful processor ever to use the RISC-V instruction set.
According to a social media post by Alibaba’s DAMO Academy, which develops some of its chips, the new XuanTie C950 is ready to power cloudy servers, generative AI workloads, high-end robotics, and edge computing devices.
“The XuanTie C950 is equipped with a self-developed AI acceleration engine, and for the first time natively supports large models with hundreds of billions of parameters, such as Qwen3 and DeepSeek V3, potentially becoming a new type of high-end CPU for the AI Agent era,” the post enthuses.
Alibaba claims the machine’s single-core general-purpose performance “exceeded 70 points in the SPECint 2006 benchmark test.” Photos from Tuesday event at which Alibaba announced the chip suggest its SPECInt 2017 benchmark result is 2.6GHz. Per analysis by Google researcher Laurie Kirk puts it nearly on par with Apple’s M1 chip – which the iGiant launched in the year 2020.
Kirk also noted that Alibaba claimed it’s implemented version 23.1 of the RISC-V RVA, a minor update proposed in August 2025. She expressed surprise Alibaba was able to use it so quickly.
A product page and spec sheet for the chip add more details – but also omit details like core count and instead offer the non-specific description of the chip as a “64-bit multi-core CPU IP.”
Based on those documents the “acceleration engine” mentioned above is probably the XuanTie Tensor Processing Engine (TPE) and supports data types from FP16 down to INT4/FP8, plus the micro-scaling formats MXFP8, MXFP4, and RVFP4. The chip can achieve 8 TOPS per TPE.
The memory subsystem apparently “comprises a high-performance multi-level cache hierarchy with an ultralow 4-cycle load-to-use L1 data cache latency, a private per-core L2 cache supporting large capacity configurations, and an MMU with multiple RISC-V virtual memory modes and two-stage address translation.”
In a section of the spec sheet discussing buses, there’s a mention of a multi-processor mode that “leverages the XL-300 interconnect to form clusters of up to 8 cores.”
Posts The Register has seen suggest Alibaba had the chip made using a 5nm process, a feat that’s not beyond some Chinese chipmakers. Whether they can build chips of that caliber in large quantities is less certain.
Alibaba CEO Yongming Wu last week acknowledged that Chinese chips lag behind those from western chipmakers. He said the company’s response is “to engage in more profound co-design with Alibaba's cloud infrastructure and the Qwen model to provide improved cost effectiveness. This is one key differentiator … that sets us apart from other chip companies.”
So while the XuanTie C950 may not be a particularly powerful chip, and Alibaba may struggle to get millions of them into production, native support for the company’s own Qwen models suggests Wu’s vision for a nicely harmonized AI stack is becoming a reality. ®