R&D: AEIS, New Energy Efficiency Improvement Scheme for MLC STT-MRAM
Evaluation results show that AEIS can eliminate TTs in MLC STT-MRAM, reduce energy consumption by 28.5%, and increase the lifetime by 24.8%, while the total number of bits used for the cache only increases by 5.7%.

IEEE Transactions on Computers has published an article written by Dong Yin,College of Information Science and Engineering, Hunan University, Changsha, China, School of Computer and Artificial Intelligence, Huaihua University, Huaihua, China, and The Ministry of Education Key Laboratory of “Fusion Computing of Supercomputing and Artificial Intelligence”, Changsha, China, Huizhang Luo; Yan Ding; Chubo Liu; Wenchao Zhao; and Kenli Li, College of Information Science and Engineering, Hunan University, Changsha, China, and The Ministry of Education Key Laboratory of “Fusion Computing of Supercomputing and Artificial Intelligence”, Changsha, China.

Abstract: “Spin Transfer Torque-Magnetic Random Access Memory (STT-MRAM), as a new non-volatile memory technology with lower leakage power and higher density, is widely considered to be a new generation of memory technology that may replace SRAM in the cache. STT-MRAM is divided into Single-Level Cell (SLC) STT-MRAM and Multi-Level Cell (MLC) STT-MRAM. Compared with SLC STT-MRAM, MLC STT-MRAM has further improved its storage density. However, MLC STT-MRAM has a high write energy consumption and write latency due to its unique two-step state transitions (TTs) issue. State-of-the-art approaches mitigate this issue by eliminating TTs with expansion coding methods. Unfortunately, they focus more on eliminating TTs and have limited improvement in reducing energy consumption. To this end, we propose a new scheme, AEIS, which further reduces energy consumption while eliminating TTs. Our work begins with exploring the general rules of (M,N)-based expansion coding methods that eliminate TTs. Based on the discovered rules, the minimum energy coding method is found. To further improve energy efficiency, we segment the cache lines according to the data pattern. We only apply the expansion coding to those flipping segments to reduce the expansion coding overhead. The evaluation results show that AEIS can eliminate TTs in MLC STT-MRAM, reduce energy consumption by 28.5%, and increase the lifetime by 24.8%, while the total number of bits used for the cache only increases by 5.7%.“

R&D: Versatile One-Time-Programmable STT-MRAM for Security-Aware Scenario
Authors demonstrates a 96-Kb versatile MRAM-OTP macro integrated with a 6-Kb OTP-based physical unclonable function (PUF) in 55-nm fully depleted silicon on insulator process.

IEEE Transactions on Reliability has published an article written by Jiongzhe Su; Haoran Du; Mingtao Chen; Keyang Zhang; Yichen Zhu; and Quanhai Zhu, School of Integrated Circuits, Southeast University, Nanjing, China.

Abstract: “Recently, one-time-programmable (OTP) memory has been widely used in micro controller unit (MCU) due to its storage reliability and tamper-proof. Based on the analysis of the breakdown mechanism of magnetic tunnel junction and the measurement results used for modeling, this article demonstrates a 96-Kb versatile MRAM-OTP macro integrated with a 6-Kb OTP-based physical unclonable function (PUF) in 55-nm fully depleted silicon on insulator process. The MRAM-OTP macro realize minimum 3.0 V program voltage and 100 ns for 32-bit program speed. The on-chip power supply method trims with PVT variations and completes voltage switching between two modes. The multi-bit programming design saves about 97% time and 5% energy using self-termination. The discernible dual-mode sense amplifier saves 57.4% power in OTP reading with no lacks of sensing yield. We also presented the application scheme of the proposed MRAM-OTP macro within the trimming information storage and security MCU design, with the PUF helped to complete the authentication process together with OTP and the error correcting code assisted encrypting and correcting process. The trimming information can help to enhance the reliability of STT-MRAM main area. With the reconfigurable bit-cell design, the Inter-HD and Intra-HD of the OTP-based PUF can reach 49.77% and 0.08%, respectively.“

R&D: Research on Low-Power MRAM Analog and Digital In-Memory Computing
Study introduces the fundamental principles of MRAM and in-memory computing. The digital in-memory computing section covers PGU units and Python-based MRAM simulation design.

IEEE Xplore has published, in 2025 5th International Conference on Electronic Information Engineering and Computer Technology (EIECT) proceedings, an article written by Jiarui Li, Automation, School of Electronics and Information Engineering, Guangdong Ocean University, Zhanjiang, China.

Abstract: “To address the challenges posed by the “memory wall” in traditional von Neumann architectures-namely low data utilization efficiency and high power consumption-the compute-in-memory architecture has been proposed. Among its components, magnetic random-access memory (MRAM) stands out as an ideal carrier for compute-in-memory due to its non-volatility and low power consumption characteristics. This study introduces the fundamental principles of MRAM and in-memory computing. The digital in-memory computing section covers PGU units and Python-based MRAM simulation design. The analog in-memory computing section details analog in-memory computing architectures, two approaches to variable weighting, and application scenarios for analog in-memory computing.“

R&D: Time-Based Sensing With Linear Current-to-Time Conversion for Multi-Level Resistive Memory
Paper introduces a novel time-based sensing (TBS) scheme for enhancing the sensing speed and robustness for single-level cells (SLC) to multi-level cells (MLC).

IEEE Transactions on Circuits and Systems I: Regular Papers has published an article written by Byung-Kwon An; School of Electrical and Electronic Engineering, Nanyang Technological University, Jurong West, Singapore, Xueyong Zhang; School of Integrated Circuits, Southeast University, Nanjing, China, Anh Tuan Do; IC-Design Department, Institute of Microelectronics (IME), A*STAR, Fusionopolis, Singapore, and Tony Tae-Hyoung Kim, School of Electrical and Electronic Engineering, Nanyang Technological University, Jurong West, Singapore.

Abstract: “Resistive Random Access Memory (RRAM) is a promising low-power memory candidate because of a large R-ratio (RHRS/RLRS). Multi-level RRAM cells have been investigated to improve memory density and cost-per-bit. However, sensing multi-level becomes challenging due to the smaller R-ratios between stored digital values. This paper introduces a novel time-based sensing (TBS) scheme for enhancing the sensing speed and robustness for single-level cells (SLC) to multi-level cells (MLC). The proposed time-based sensing scheme converts the bit line (BL) current into a time delay using a novel current-to-time converter (CTC). The BL-current-dependent time delays are utilized to generate digital data. In addition, the proposed sensing scheme executes sensing without need for reference current or reference voltage. Comprehensive simulation in 40nm CMOS technology shows that the proposed TBS scheme achieves better linearity and higher read speed by precise cell current replication in CTC compared to the prior TBS schemes. As a result, the proposed TBS reduces sensing latency by 230%~340% compared to the prior TBS schemes. Furthermore, the proposed TBS improves the variation tolerance of read operation by 5%~33% at 1.1 V.“

R&D: High-Accuracy, High-Performance In-Memory Computing With High-Resistance Spin-Orbit Torque (SOT) Magnetic Memory
Authors provide a detailed statistical characterization of SOT-MRAM arrays and develop quantization-aware training of various neural networks.

IEEE Transactions on Electron Devices has published an article written by F. Carletti, Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB), Politecnico di Milano and IU.NET, Milan, Italy, M. Y. Song, E. Ambrosi, C. Y. Hu, C. F. Hsu, Taiwan Semiconductor Manufacturing Company, Corporate Research, Hsinchu, Taiwan, P. Mannocci, Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB), Politecnico di Milano and IU.NET, Milan, Italy, G. L. Chen, I. J. Wang, K. M. Chen, Y. C. Hsin, Industrial Technology Research Institute, Hsinchu, Taiwan, M. Farronato, Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB), Politecnico di Milano and IU.NET, Milan, Italy, X. Y. Bao, Taiwan Semiconductor Manufacturing Company, Corporate Research, San Jose, CA, USA, and D. Ielmini, Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB), Politecnico di Milano and IU.NET, Milan, Italy.

Abstract: “In-memory computing (IMC) has emerged as a promising solution for artificial intelligence (AI) accelerators due to the reduced data movement and improved parallelism in the crosspoint array. However, IMC faces several limitations such as the device variations affecting the computing accuracy, the area- and energy-consuming peripheral circuitry, and the time-consuming high-voltage program-verify operations of the nonvolatile memory (NVM). In addition, the relatively large summation currents cause IR drop within the array, leading to further loss of accuracy. To overcome these issues, this work presents 1-bit quantized networks based on spin-orbit-torque magnetoresistive random access-memory (SOT-MRAM) with high resistance–area (RA) product. We provide a detailed statistical characterization of SOT-MRAM arrays and develop quantization-aware training of various neural networks. Our results indicate that SOT-MRAM enables: 1) high inference accuracy, thanks to excellent uniformity; 2) negligible input-dependent IR drop nonlinearity, thanks to high resistance; and 3) high-speed, low-power reconfiguration, thanks to fast device programming. These results support high-RA SOT-MRAM for digital-like and reconfigurable IMC accelerators of edge AI.“