NextSilicon, a active player in next-generation computing solutions for AI and HPC, announced plans to productize its Arbel RISC-V core into a 64-core and a 128-core, enterprise-grade processor suited to deliver ultra-speed performance for agentic tools, expected to be available in early 2028.Following an October preview, the company is now sharing expanded technical detail and a roadmap shaped by early customer and partner feedback. This announcement coincides with NextSilicon’s presentation at the RISC-V Summit.

NextSilicon designed Arbel from the ground up for the performance demands of AI infrastructure and HPC. The move from test chip to production roadmap follows customer and partner silicon evaluations, including HPC program leads, AI infrastructure architects, and data center operators. Their input has validated Arbel’s key performance attributes and is shaping the requirements and architecture decisions for the 64-core production processor.

Introducing Arbel: Silicon-Proven, Customer-Validated
Arbel exists because NextSilicon needed a core that could keep up with the rest of the system. The company originally designed it as the control processor inside its Maverick-2 accelerator platform, where it handles the serial logic and data movement that the dataflow engine cannot parallelize. That production deployment became the proving ground: the core had to perform under real workload conditions, not just pass a benchmark suite.

NextSilicon fabricated a standalone Arbel test chip on TSMC’s 5nm process to validate the architecture outside the accelerator context as a full evaluation system. The results confirmed what the Maverick-2 deployment had already demonstrated. A 10-wide instruction-issue pipeline and 480-entry reorder buffer deliver up to 16 scalar instructions per cycle at retirement. Four 128-bit vector units handle data-parallel workloads, including AI inference. Clock speeds reach 2.5 GHz. Standard coherent CHI interconnect and full Linux OS support make the core a practical candidate for server and HPC system evaluation.

Customer and partner evaluations of the test chip silicon validated those performance characteristics and shaped the requirements for the production processor. That feedback drove the decision to productize Arbel as a standalone 64-core server chip, detailed in the next section.

Taking Arbel from Test Chip to Production
The production processor scales the Arbel architecture to 64/128 performance cores, targets a 3.4 GHz operating frequency, and moves to a more advanced process node to meet the power efficiency and density requirements of production data center and HPC deployments. The core architecture retains the defining characteristics of the test chip, including the TAGE branch predictor designed for competitive prediction accuracy against the leading x86 and ARM server implementations.

The chip targets two complementary deployment roles. As a standalone enterprise server processor, it offers organizations a high-performance RISC-V alternative designed to reduce ISA licensing constraints and long-term dependence on third-party vendor roadmaps. As a host processor for NextSilicon’s Maverick accelerator platform, it handles system orchestration and data movement for heterogeneous AI and HPC deployments. Both roles are supported by full RVA23 compliance and standard Linux distribution support.

“Agentic AI changes the game. The future isn’t just more accelerators – it’s smarter, more powerful CPUs with fewer, stronger cores. The response from our early customers and partners has been clear: the architecture performs, and they want to see it at production scale,” said Elad Raz, CEO and co-founder, NextSilicon. “We built Arbel because Agentic AI changes what a CPU needs to do. As AI agents call more tools, trigger more code, orchestrate more services, and move through more complex workflows, the CPU can no longer be an afterthought. It needs to run fast, respond quickly, and keep the entire system moving.”

With Arbel, NextSilicon started from the workload requirements, not from the constraints of an inherited architecture. The result is a CPU designed for the next generation of AI and HPC systems, built on an open ISA that gives customers control.

“RISC-V is the most compelling architecture for the future of AI, data center, and HPC workloads,” said Andrea Gallo, CEO, RISC-V International. “We are excited to see the innovation and success of the Maverick-2 accelerator and Arbel test chip, and look forward to future developments, including RVA23 compliance.”

The RISC-V Data Center Opportunity
RISC-V has crossed the threshold from an academic architecture to a viable enterprise platform. As ecosystem standards have matured, software vendors increasingly have stable, consistent targets to build and certify against – similar to the foundation that drove broad adoption of x86 and ARM in data centers. Major Linux distributions, compiler toolchains, and systems software now support RISC-V natively, with ecosystem support from Canonical, Red Hat, and NVIDIA. The data center and HPC segment of the RISC-V market is projected to expand at a compound annual growth rate of 33.1% from 2025 to 2034 to over $200B.

The gap that remains is at the top of the performance envelope. HPC and AI workloads are hybrid. They require massive parallelism for compute-intensive segments, combined with serial control logic that determines the throughput ceiling of the entire system. Agentic AI coding platforms represent a fast-growing example of this architectural mismatch. Unlike training workloads that scale across thousands of GPU cores, agentic coding tasks run autonomous reasoning loops that are fundamentally serial: parsing code context, evaluating alternatives, generating and validating output.

These workflows demand strong single-thread performance from a compact core alongside integrated acceleration for inference, not the wide, general-purpose server cores designed for cloud multitenant scheduling. As agentic workloads scale from developer tools to enterprise infrastructure, the gap between what cloud CPUs were designed for and what these workloads actually need will widen. That serial path requires a CPU designed for maximum single-thread execution speed, not a general-purpose core managing system overhead. No existing RISC-V processor was built with that specific requirement as the primary design constraint. Arbel was.

Availability and Customer Engagement
The Arbel production processor is expected in Q1 2028. NextSilicon is engaging qualified customers now for early access discussions and continued roadmap collaboration. Organizations evaluating RISC-V infrastructure for HPC or AI applications can contact NextSilicon to discuss workload requirements and options.

NextSilicon will present a detailed technical overview of the Arbel architecture and production roadmap at the RISC-V Summit on June 10, 2026.