Systems

Chinese tech biz shows off clever workaround for its process node gap, but it isn't catching up with Intel and TSMC

Huawei is touting a semiconductor advance - including something it calls the "Tau Scaling Law" as a successor to Moore's Law - but at least one chip expert says the news is more branding than breakthrough.

The Chinese tech titan unveiled its advances at the 2026 IEEE International Symposium on Circuits and Systems (ISCAS) in Shanghai during a speech titled "New Semiconductor Path in Practice" by He Tingbo, president of its semiconductor business.

He, who is a she, said Moore's Law has seen diminishing returns, and instead presented the Tau Scaling Law as "a new principle for guiding the future development of the semiconductor industry."

Tau Scaling, according to He, is about "a shift from geometric to time scaling as the new guiding principle for electronic system evolution." She said that, at the device level, this is about signal propagation time, which is linked to interconnect RC (resistance and capacitance) parasitics, pipeline length, and circuit depth.

In other words, it is about optimizing the resistance and parasitic capacitance of transistors and interconnects to cut signal delays, which every chip company puts a lot of effort into anyway.

As an example of how Tau Scaling works, He said LogicFolding is one solution Huawei has devised - set to feature in its Kirin 2026 system-on-chip, the latest version of its silicon for smartphones, later this year.

"It is built on a brand-new free logic design concept, expanding from a single-layer to a double-layer architecture," He said, meaning that it stacks transistors into two layers. A similar-sounding technology has also been the subject of research by Intel and TSMC.

"Before LogicFolding, it took three years to lift transistor density from 126 to 155 MTr/mm² [million transistors per square millimeter]. In 2026, LogicFolding takes it all the way to 238 MTr/mm², in one single step," according to He.

Huawei claims its high-end chips based on the Tau Scaling Law are expected to feature a transistor density that is equivalent to a 14 Angstrom (1.4 nm) manufacturing process by 2031.

But Manoj Sukumaran, senior principal analyst at Omdia, poured cold water on Huawei's claims.

"The '14 angstrom equivalent by 2031' is not a process-node claim. Huawei is stuck on 7nm. They're hybrid-bonding logic dies on top of each other, so projected area halves and equivalent density rises. That's density achieved though clever packaging, not transistor shrinking, and is not comparable to a real TSMC/Intel 1.4nm transistor," he told The Register.

Intel expects to introduce its 14A 1.4nm chip process in 2028, with volume production in 2029, CEO Lip-Bu Tan said recently, and TSMC is operating on a similar timescale.

"I feel the key gains (~12.7 percent performance, ~41 percent efficiency) could be real, but it is likely to come from shorter interconnect and clock trees, not the transistor, which is also why they never mention leakage," Sukumaran added.

"Huawei had to get creative and they are in the right direction on that front. They presented a clever but costly workaround for a node gap under sanctions. But it also has a ceiling: each added stacking layer gives diminishing returns."  ®