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Latest from Tom's Hardware in Semiconductors

Post-silicon era gets closer as industry giants crack the 2D transistor scaling bottleneck with breakthrough tech — imec, ASML, and TSMC fab complementary 2D-material transistors at 50nm pitch on a 300mm wafer Intel Intel’s performance-enhanced 18A-P process enters risk production — drop-in 18A upgrade promises 9% performance improvement at iso-power, cuts thermal resistance by 40% Chinese fab SMIC TSMC says panel packaging won Analyzing TSMC's fab expansion roadmap — multi-fab N2 ramp, CoWoS, SoIC, and uncorking bottlenecks Chinese startup claims photonic chip production without DUV lithography, says nanoimprint process cuts costs by 90%… ASML becomes Europe's most valuable company ever as analysts bet on higher EUV output — its market cap hit… TSMC CEO C.C. Wei says, ‘It will be a long time before we can meet customer demand’ — tells shareholders that he will keep prices stable, refrain from implementing price hikes Samsung shows first HBM5 mockup with Heat Path Block cooling — thermal race with SK hynix shaping up Seven hospitalized after toxic gas fire at SK hynix advanced memory plant — Cheongju 4th campus incident today led… TikTok owner ByteDance is reportedly developing its own custom AI CPUs — company looks to ease China's… Trailing-edge foundry roadmaps for GlobalFoundries, UMC, and SMIC — mature node chipmakers each pursue differing… Chinese university builds 3D chip design tool tailored to Huawei's ‘LogicFolding’ architecture — 3D design delivers increased performance and better thermal management China adds homegrown AI chips to 'secure and reliable' procurement list for the first time — nine options added as move away from Nvidia continues SK hynix unveils 'iHBM' thermal architecture that cools AI memory at the source — integrated cooling elements inside HBM interface cut thermal resistance by 30%, target next-gen HBM5 accelerators and dense AI data centers Imec builds world's first High-NA EUV-fabricated quantum dot qubit device — breakthrough could pull quantum computing onto the same manufacturing roadmap as next-gen AI processors, compressing timelines Huawei claims sanctions-busting breakthrough with 1.4nm-class chips by 2031, claims 55% higher transistor density — firm claims new LogicFolding chip architecture can bypass EUV restrictions, introduces 'Tau Scaling Law' to replace Moore's Law Samsung's $400,000 payout for memory workers sparks revolt as other divisions get only $4,000, fueling intentional production slowdowns — internal resentment disrupts packaging operations, major AI chip project decisions to a complete halt The custom AI ASIC state of play (May 2026) — Broadcom deals, Google TPUs, Meta MTIA & beyond AMD begins production ramp of 256-core EPYC Venice — first 2nm HPC chip claims 70% performance leap Intel kicks off development on next-decade 10A and 7A process technologies — 14A node remains on track for… SMIC founder and AMEC CEO urge Chinese fabs to test domestic chipmaking tools on active production lines — equipment makers post record revenue but falling margins Russia’s Mikron is selling framed test wafers with up to 120,000 processors as souvenirs — 12 designs, priced around $170 each, sold alongside $2 vials of cleanroom air Trump calls $14 billion Taiwan arms deal a 'negotiating chip' with China after Xi said Taiwan issue could lead to 'clashes and even conflicts' — Trump says 'Taiwan would be very smart to cool it a little bit' Leading-edge foundry roadmaps for TSMC, Intel and Samsung — outlining the path to 1.4nm nodes and beyond TSMC allocates $20 billion to Arizona expansion — project faces water and labor shortages, complicated by visa… NASA partners with Microchip to build next-generation spaceflight chips with 100x the power of current offerings — chip designed to withstand radiation for extended missions on the Moon and Mars Intel, SK hynix shares surge following reports of chip packaging partnership — SK is said to be testing… Apple reportedly strikes deal for Intel to make some of its chips — two tech giants reached a preliminary…
Enthusiast builds his own RAM in garden shed cleanroom &m...
https://www.tomshardware.com/author/mark-tyson · 2026-04-22 · via Latest from Tom's Hardware in Semiconductors
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(Image credit: Future)

Dr. Semiconductor is back in his shed, and this time he’s checking whether Joe Public can DIY themselves out of the DRAM crisis. In the video embedded below, you can see the good doctor go through the semiconductor process steps required to make an array of memory cells in a backyard shed cleanroom. This is the “first time ever RAM has been made at home,” boasts our hero.

— Making RAM at Home

RAMageddon isn’t the only issue affecting PC DIYers and the industry in general. Dr. Semiconductor mentions the AI-industry-fueled RAM price disruption being driven by the big three players (but there are others) not being able to keep up with demand. We are seeing similar effects on storage, GPUs, and some reckon CPU supplies will also begin to be impacted.

With the existing industry incapable of addressing consumer RAM needs at attractive prices in 2026, the TechTuber asks, “I turned a shed in my back yard into a class 100 semiconductor cleanroom… but the question is, can I make my own RAM?”

After the intro, Dr. Semiconductor gives a brief description of how computer memory works, and how it is largely made up of huge arrays featuring oodles of capacitors and transistors.

Moving on to the practicalities of the job at hand, the good doctor begins by snipping a couple of silicon chips from a large sheet. This is the beginning of the preparation and cleaning stage of the chipmaking process.

Next up, we move to the initial patterning stage. A layer of oxide is built on the surface of the silicon in a high-temperature furnace. It is estimated that this layer is 330nm thick. On top of this layer, an adhesive layer and photoresist film are applied. UV exposure projects a design mask onto this newly created surface, which allows a developer solution to wash away the areas that have been hit by the light rays.

The source and drain of the transistors in the design are formed in the following steps. This involves more layer etching, doping exposed silicon to make it highly conductive, then annealing the chips to push the doping agent deeper.

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Several more carefully targeted deposition and erosion steps later, we are ready for the metallization of the silicon chip. A tiny stencil is used to accurately spray the sample with aluminum, the excess stripped away, and the fully layered and formed chip is at last ready for some tests!

Checking the results

The freshly fabricated DRAM cells are so small that wires can’t be used to hook them up to test machinery by the DIYers. Micromanipulator probes are precisely positioned instead. The good news is that Dr. Semiconductor was pleased with his finished DRAM chips, as cells were measured to offer a hobbyist sweet spot of 12pF capacitance.

At the end of the video, the doc teases that he’s going to build on this significant, though admittedly small-scale, achievement. He’s looking to prepare a much larger array of finished memory cells and says that they will be prepared to “hook up to a PC.” Stay tuned for the PC-scale practical implementation, folks.

We reported on Dr. Semiconductor's creation of this garden shed-based cleanroom back in March.

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Mark Tyson is a news editor at Tom's Hardware. He enjoys covering the full breadth of PC tech; from business and semiconductor design to products approaching the edge of reason.