Low complexity error correction code is a key enabler for next generation ultra-reliable low-latency communications (xURLLC) in six generation (6G). Against this background, this paper proposes a decoding scheme for linear block code by leveraging certain interesting properties of dual codewords. It is found that dual codewords with flexible weights can provide useful decoding information for the locations and magnitudes of error bits, which yielding higher reliability performance. In addition, two decoding schemes are proposed, in which one directly utilizes intrinsic information for iterative decoding, and the other combines prior channel information with intrinsic information for decoding. Both schemes are implemented using vector multiplication and real-number comparisons, making them easy to implement in hardware. Simulation results demonstrate the validness of our study.